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fir4btp
4tap FIR filter in verilog code
- 2014-01-13 22:30:58下载
- 积分:1
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eetop.cn_dds
基于verilog的DDS设计,内附代码,仿真环境等说明(the DDS design based on verilog)
- 2015-07-14 08:20:51下载
- 积分:1
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shizhong
VHDL写时钟,分频模块什么,实现计时。定点报时,定点闹钟,显示年月日。(verilog HDL)
- 2014-01-09 18:29:40下载
- 积分:1
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FDDDDRSDRAMP
一种基于FPGA 实现DDDR SDRAM的控制器
(DDDR SDRAM controller based on FPGA)
- 2012-08-29 23:52:53下载
- 积分:1
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zedboard
xilinx的zed板详细开发资料,对初学者和开发人员都有帮助(The Xilinx zed board detailed development information, helpful for beginners and developers)
- 2013-04-22 16:44:31下载
- 积分:1
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实现在屏幕上显示绿色和红色相间的水平条纹
实现在屏幕上显示绿色和红色相间的水平条纹。其中,vga_640x480模块将产生行同步信号hsyn和场同步信号 vsync; vga_stripes模块将产生red、green和blue三个输出。(The horizontal stripes of green and red are displayed on the screen. Among them, vga_640x480 module will produce line synchronization signal Hsyn and field synchronization signal vsync; vga_stripes module will produce red, green and blue three outputs.)
- 2020-06-24 02:00:02下载
- 积分:1
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QC_LDPC_FPGA
LDPC QC-LDPC 基于FPGA的QC-LDPC实现 论文(LDPC QC-LDPC FPGA-based QC-LDPC detailed implementation steps
Thesis)
- 2021-04-08 09:29:00下载
- 积分:1
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fdivision
在quartus平台下,并使用verillog hdl编写的时钟分频仿真(In quartus platform and use verillog hdl write clock divider simulation)
- 2016-08-15 07:45:12下载
- 积分:1
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usbFPGAconnect
该例程是PC机通过FX2-CY7C68013-A的USB2.0控制芯片与FPGA实现通信。其中的工程和代码包括PC机上的USB固件程序、驱动程序、上位机程序,FPGA上的VERILOG通信程序。(The routine is a PC, through the FX2-CY7C68013-A of the USB2.0 controller chip and the FPGA to achieve communication. One of the projects and code, including PC, the USB firmware, drivers, FPGA' s Communication Program)
- 2021-04-08 15:19:00下载
- 积分:1
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cic_compensating
CIC 补偿滤波器。采用两种方法来设计,一个是frequency sampling method。另一个是Equal Rippler Design Method。这是一个非常有用的matlab代码。(CIC compensation filter. Two ways to design a frequency sampling method. The other is an Equal Rippler Design Method. This is a very useful matlab code.)
- 2012-10-17 14:22:08下载
- 积分:1