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基于verilog的LZS压缩和解压算法
基于verilog的LZS压缩和解压算法，压缩比1；2 。里面带有C原言的代码。已经通过验证！(Verilog based LZS compression and decompression algorithm, compression ratio 1; 2. It has the C code in it. It has been verified!)
- 2018-07-23 10:35:55下载
- 积分：1
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lcd-ip-core
LCD 驱动的IPCORE，可用于alteraFPGA(LCD driver IPCORE, can be used to alteraFPGA)
- 2011-02-15 11:34:38下载
- 积分：1
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apb_spi
Simple SPI interface realization on Verilog HDL with parameterized FIFO and APB interface
- 2021-04-06 16:19:02下载
- 积分：1
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cfg9230
ad9230的配置程序，差分输入输出，verilog(ad9230 configuration program, verilog)
- 2021-03-18 19:09:19下载
- 积分：1
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TEXTIO_Import_txt_Matlab
将FPGA设计仿真结果数据写入到txt记事本中，然后通过Matlab读取txt中的数据并显示图像(write the FPGA simulation result data into textbook,and read these data from textbook and display image in Matlab)
- 2012-12-28 13:42:57下载
- 积分：1
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DC-DC
/功 能：1.实现与CPLD的通信,从而控制PWM的占空比. 2.实现LCD显示相关信息.
// 3.实现对键盘按键的判断和确定相应的操作. 4.实现对电压电流的检测.
// 5.实现过载保护功能,电流过大时,切断PWM输出,当排除过流故障后,自动恢复供电
// 6.实现用PID算法跟踪电压,实现稳压输出(/ Function: 1. Achieve communication with the CPLD to control the PWM duty cycle. 2 LCD Display relevant information.// 3. Realize the keyboard keys judgment and determine the appropriate action. 4. Achieve the voltage and current Detection// 5. achieve overload protection, current is too large, cut off the PWM output, when excluding overcurrent fault, automatically restore power// 6. achieve tracking voltage with PID algorithm to achieve the regulated output)
- 2013-05-23 16:28:30下载
- 积分：1
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AXI slave verilog 代码
自己写的 AXI slaver verilog code，希望带给大家一些启示
- 2022-07-23 07:27:26下载
- 积分：1
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FIR_filter
滤波器就是对特定的频率或者特定频率以外的频率进行消除的电路，被广泛用于通信系统和信号处理系统中。(Filter is a circuit that eliminates specific frequencies or frequencies other than specific frequencies. It is widely used in communication systems and signal processing systems.)
- 2020-06-21 14:00:01下载
- 积分：1
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clock
软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 多功能数字钟(Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.0 1. Multi-function digital clock)
- 2009-03-22 12:44:34下载
- 积分：1
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can-lite-vhdl-master
说明： CAN VHDL Code. Behavioral implementation of CAN bus interface.
- 2021-01-19 21:48:41下载
- 积分：1
