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ofdm的verilog程序
利用ＦＰＧＡ实现
ofdm的verilog程序
利用ＦＰＧＡ实现-OFDM FPGA using the Verilog procedures realize
- 2022-08-07 01:11:15下载
- 积分：1
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bit
// Data port, granularity 8
// -*- Mode: Verilog -*-
// Filename : wb_master.v
// Description : Wishbone Master Behavorial
// Author : Winefred Washington
// Created On : 2002 12 24
// Last Modified By: .
// Last Modified On: .
// Update Count : 0
// Status : Unknown, Use with caution!
// Description Specification
// General Description: 8, 16, 32-bit WISHBONE Master
// Supported cycles: MASTER, READ/WRITE
// MASTER, BLOCK READ/WRITE
// MASTER, RMW
// Data port, size: 8, 16, 32-bit
// Data port, granularity 8-bit
// Data port, Max. operand size 32-bit
// Data transfer ordering: little endian
// Data transfer sequencing: undefined-//-*- Mode: Verilog-*-
// Filename : wb_master.v
// Description : Wishbone Master Behavorial
// Author : Winefred Washington
// Created On : 2002 12 24
// Last Modified By: .
// Last Modified On: .
// Update Count : 0
// Status : Unknown, Use with caution!
// Description Specification
// General Description: 8, 16, 32-bit WISH
- 2023-03-16 01:05:04下载
- 积分：1
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HART-HT2015
HART 官方资料-HART协议采用基于Bell202标准的FSK频移键控信号，在低频的4-20mA模拟信号上叠加幅度为0.5mA的音频数字信号进行双向数字通讯，数据传输率为1.2kbps。(Official information-HART HART protocol based Bell202 standard frequency shift keying FSK signal at low frequencies 4-20mA analog signal amplitude is 0.5mA superimposed on the two-way audio digital signal digital communication, data transfer rate of 1.2kbps.)
- 2013-07-16 17:23:16下载
- 积分：1
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chuankou
本实验为UART回环实例，实验程序分为顶层unrt_top、发送模块uart_tx、接收模块 uart_rx，以及时钟产生模块clk＿div。uart＿rx将收到的包解析出8位的数据，再传送给 uart_tx发出，形成回环。参考时钟频率为100MHz，波特率设定为9600bps。(This experiment is an example of UART loop. The experimental program is divided into top-level unrt_top, sending module uart_tx, receiving module uart_rx, and clock generation module clk_div. Uart_rx parses the received packet into 8 bits of data and sends it to uart_tx to send out, forming a loop. The reference clock frequency is 100 MHz and the baud rate is set to 9600 bps. stay)
- 2020-06-24 01:40:02下载
- 积分：1
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this a fpga sparttan 3e based project in which
i have made a game based on vg...
this a fpga sparttan 3e based project in which
i have made a game based on vga interface .
this file is the supporting file for ps/2 interface .-this is a fpga sparttan 3e based project in which
i have made a game based on vga interface .
this file is the supporting file for ps/2 interface .
- 2022-05-21 12:25:58下载
- 积分：1
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一个完整的viterbi译码程序和测试的程序
一个完整的viterbi译码程序和测试的程序-A complete viterbi decoding procedures and test procedures
- 2023-01-14 14:40:03下载
- 积分：1
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Quartus_17.1破解器_Windows_密码12345
quartus 17.1 安装包，我现在用的就是(Quartus 17.1 installation kit, what I am using now is)
- 2018-09-10 20:13:45下载
- 积分：1
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带自适应波特率发生器UART实现，经过FPGA验证的！
带自适应波特率发生器UART实现，经过FPGA验证的！-UART baud rate generator with adaptive realization, after FPGA validation!
- 2023-01-21 06:20:04下载
- 积分：1
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bubblesort1024ram
说明： 快速冒泡排序基于FPGA实现，有测试文件以及设计图，实现1024*32位数序的多数排序，突破传统是的REG类型少数排序，利用RAM，针对RAM中的无序数的地址调换，达到排序目的，仅供学习交流(Rapid bubble sort based on FPGA, there are test documents and design drawings to achieve 1024* 32-digit sequence of the majority of sorting, breaking tradition is a REG types of minority sorting, the use of RAM, the disorder for the RAM address of the number of exchange, to sort purpose, only to learn the exchange of.)
- 2010-03-24 15:19:50下载
- 积分：1
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agc_gen
AGC(自动增益放大) Verilog代码 设计可以参考(AGC (automatic gain control) can refer to the Verilog code design
)
- 2015-04-14 01:16:13下载
- 积分：1
