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rs_enc
Verilog code for RS-(255,239) encoder.
- 2021-04-06 16:19:02下载
- 积分：1
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fir.tar
FIR滤波器的VHDL语言实现(The implement of FIR Filter based on VHDL)
- 2004-10-19 10:14:56下载
- 积分：1
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control_s
数控机床 多轴插补原理积分算法，实现s曲线加减速原理(Numerical control machine tool multi axis interpolation principle, integration algorithm, to achieve the S curve acceleration and deceleration principle)
- 2021-05-07 09:58:36下载
- 积分：1
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FPGA实验，实现了蜂鸣器发出不同的音调，利用按键，很好玩的...
FPGA实验，实现了蜂鸣器发出不同的音调，利用按键，很好玩的-FPGA experiment, realized the buzzer sounded a different tone, the use of keys, it is fun
- 2022-07-24 17:58:54下载
- 积分：1
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veval
It is vhdl code for defining a finite state machine
- 2009-08-07 18:06:13下载
- 积分：1
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arm
ARM教程,理解精辟，言简意赅，不错哦，欢迎大家看看(arm language )
- 2009-02-18 20:06:42下载
- 积分：1
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cadence verilog lanaguage and simulation course
cadence verilog lanaguage and simulation course
- 2022-03-03 00:45:22下载
- 积分：1
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本文是自已写的电子密码锁的详细开发过程，用的是Modelsim进行仿真实现，打开文档lzp...
本文是自已写的电子密码锁的详细开发过程，用的是Modelsim进行仿真实现，打开文档lzp-This article is written in their own electronic locks detailed development process, using a ModelSim simulation achieved, open the document lzp
- 2022-01-25 15:10:58下载
- 积分：1
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开发系统上采用的时钟信号的频率是20MHz，可分别设计计数器对其计数，包括计秒、分、小时、日、周、月以及年等。在每一级上显示输出，这样就构成了一个电子日历和时钟...
开发系统上采用的时钟信号的频率是20MHz，可分别设计计数器对其计数，包括计秒、分、小时、日、周、月以及年等。在每一级上显示输出，这样就构成了一个电子日历和时钟的模型。为了可以随意调整计数值，还应包含设定计数初值的电路-Development system using the clock signal frequency is 20MHz, the design can be counter to its count, including seconds, minutes, hours, days, weeks, months and years. At every level to show the output, thus constitutes an electronic calendar and clock models. Can also adjust the order value, should also be included in setting the initial count circuit
- 2022-08-07 06:47:58下载
- 积分：1
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应用硬件描述语言产生随机数，在模糊控制仿真中应用的较多...
应用硬件描述语言产生随机数，在模糊控制仿真中应用的较多-By VHDL generating random Numbers, in the application of the fuzzy control simulation
- 2022-06-15 20:13:25下载
- 积分：1
