8051 Core FPGA verilog 完整

代码说明：

应用背景Logical separation of program and data memory All 8051 devices have specific memory organization, they have separate address spaces for Program (ROM) and Data (RAM) Memory. This logical separation of Memory is useful because it allows the Data Memory to be accessed by 8-bit addresses, which can obviously be more quickly stored and manipulated by an 8-bit CPU. Of course, the l6-bit Data Memory addresses can still be generated with the DPTR register. Program Memory Program Memory can only be read, not written to. The address space for 8051 core is 16- bit, so there is maximum of 64K bytes of Program Memory. Up to 4 Kbytes of Program Memory can be on chip, internal Program Memory of the 8051 core. For access to external Program Memory is used signal PSEN (Program Store Enable). Data Memory Data Memory is on a separate address space than Program Memory. For external Data Memo