-
weifenqi
微分器:利用数字锁相环进行位同步信号提取的关键模块(Differentiator: the use of digital phase-locked loop for bit synchronous signal extraction of key modules)
- 2020-12-01 10:39:28下载
- 积分:1
-
dossvga
dos下的svga图形库,包括读bmp位图,打点划线等(svga graphics library under dos)
- 2015-10-18 22:30:38下载
- 积分:1
-
LCD1602
这是一个LCD1602底层驱动代码,TI公司LM3S系列的(This is a LCD1602 underlying driver code, TI company LM3S series)
- 2013-10-30 16:40:45下载
- 积分:1
-
8832135
一个具有“百分秒,秒,分”计时功能的数字跑表,可以实现一个小时以内的精确至百分之一秒的计时。
数字跑表的显示读者可以通过编写数码管显示程序来实现,本训练只给出数字跑表的实现过程。
读者还可以通过增加小时的计时功能,实现完整的跑表功能。(A " percentage of seconds, seconds, minutes," digital stopwatch timer can be achieved within an hour of precision to the hundredth of a second time. Digital stopwatch readers can display the digital display through the preparation of procedures to achieve, given the training is only the realization of the process of digital stopwatch. Readers can also function to increase hours of time to achieve full stopwatch function.)
- 2009-04-09 13:20:35下载
- 积分:1
-
ADC_TCL5510-verilog
verilog 驱动TLC5510代码,TLC5510是高速的AD,可达20MHz(verilog code driven TLC5510, TLC5510 is a high-speed AD, up to 20MHz)
- 2020-08-13 21:28:29下载
- 积分:1
-
四位密码锁
4位密码锁,可设置密码,三次密码错误后,锁死,密码错误报警,密码错误红灯亮,密码正确绿灯亮,基于FPGA实现,Cyclone II EP2C35F672C6 仅供参考
- 2022-01-26 07:59:07下载
- 积分:1
-
RS
通过verilog hdl语言实现RS编码器与译码器的设计(Verilog hdl language through the RS encoder and decoder design)
- 2021-04-28 15:48:44下载
- 积分:1
-
IRIG_DC_Decoder
IRIG_B解码器,直接解码IRIG_B DC(IRIG_B decoder)
- 2021-04-09 16:58:59下载
- 积分:1
-
Ver_I2C_eeprom
用verilog编写的I2C——E2PROM模型。适用于各种型号的E2PROM,代码内部有参数可选。(Written in verilog I2C- E2PROM model. E2PROM, the internal code applicable to various types of optional parameters.)
- 2013-04-10 16:14:03下载
- 积分:1
-
1151175
Image Embedded VHDL Code by using watermarking technique
- 2013-03-14 16:53:07下载
- 积分:1