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frequency divider
FPGA对系统50M时钟进行分频。FPGA最基本功能基础(FPGA Verilog program, key detection, program jitter elimination, jitter elimination, delay detection keys)
- 2019-04-27 23:35:12下载
- 积分:1
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32bit_multiply
包含32为乘法器的设计,用verilog语言实现,包括booth编码的实现,booth乘法器的实现,3_2压缩器的实现,4_2压缩器的实现,华伦斯树的实现,以及两个testbench文件用于测试。(Contains 32 multiplier design, verilog language, including booth encoding implementations, booth multiplier implementations, 3_2 compressor implementation 4_2 compressor to achieve and realize China Clarence tree, and two testbench file with the to the test.)
- 2015-01-18 21:20:48下载
- 积分:1
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CLA Verilog代码
先行进位加法器(CLA)代码的Verilog〜它包括测试平台我希望这将有助于你
- 2022-02-03 21:42:16下载
- 积分:1
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VHDL-100-examples
VHDL 的100例程代码,能够使你熟练掌握VHDL语言的编写(100 routines of VHDL code, enabling you to master the preparation of the VHDL language)
- 2012-07-31 11:17:51下载
- 积分:1
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frequency-digital-phase-measuring-
低频数字式相位测量仪,数码管显示相位差,精度为0.1(Low frequency digital phase measuring instrument, digital pipe display phase difference
)
- 2011-08-10 00:45:49下载
- 积分:1
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i2c的systemverilog vip,功能齐备,架构简洁
i2c的systemverilog vip,功能齐备,架构简洁她是用SystemVerilog写的验证模型,支持master和slave模式,支持stop bit和start bit的产生
- 2022-07-06 10:34:50下载
- 积分:1
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FLASH_PCB
M25P64-SPI-FLASH芯片的FPGA控制程序,已仿真验证(M25P64- SPI- FLASH chip FPGA control program, simulation)
- 2020-08-28 16:48:12下载
- 积分:1
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daojishi
用VHDL实现60秒倒计时的功能
倒计时为0时蜂鸣器持续响起(Continued sounded to achieve 60 seconds of the countdown function with VHDL countdown to the 0:00 buzzer)
- 2021-05-07 07:28:36下载
- 积分:1
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NAND_flash_verilog_vhdl
很好的NAND Flash 硬件驱动语言,支持VHDL和verilog 语言方便移植,如果有想用FPGA直接驱动NAND flash而又不知如何下手的朋友肯定喜欢。(NAND Flash Controller Reference
This reference design is used to interface a NAND Flash device and provides a simple host end interface. The host
end interface of this design is user-configurable. It provides buffer select signal, buffer write enable signal, address
bus, data bus, error status signal, control and handshake signals for the user......)
- 2021-03-08 22:59:28下载
- 积分:1
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fpga emif verilog
接口模块,通过对高位地址的编码可实现在一个FPGA中配置四个独立的功能模块,每个功能模块具有一个
带FIFO的输出口和13个独立的可由DSP读写的寄存器,寄存器功能可自定义。模块还包含两个全局寄存器,
可实现全局复位,中断等功能。该
- 2022-02-21 22:19:00下载
- 积分:1