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High Speed dd
(Springer Series in Advanced Microelectronics 51) Ayan Palchaudhuri, Rajat Subhra Chakraborty (auth.)-High Performance Integer Arithmetic Circuit Design on FPGA_ Architecture, Implementation and Desig
- 2020-06-24 08:40:01下载
- 积分：1
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line_four
利用verilog HDL逐点比较法实现直线和圆弧插补(Use verilog HDL by-point comparison method to achieve linear and circular interpolation)
- 2020-12-01 14:59:27下载
- 积分：1
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GgmsskModulatM
GMSK的调制解调，理理想信道，画出其功率谱。
(GMSK modulation and demodulation, management ideal channel, to draw its power spectrum.)
- 2020-07-02 02:00:02下载
- 积分：1
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UART_CESHI
基于VHDL语言的串口发送和接收程序,自己调试通过，并已经运用在工程中(Based on the serial port to send and receive procedures VHDL language, its own debugging, and has been used in the project)
- 2016-08-05 15:27:54下载
- 积分：1
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信号完整性，设计FPGA的基础
信号完整性，设计FPGA的基础-signal integrity, design based FPGA
- 2022-09-25 03:05:03下载
- 积分：1
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二进制神经网络（BNN）bnn-fpga-master
说明： bnn-fpga是FPGA上CIFAR-10的二进制神经网络（BNN）加速器的开源实现。 加速器针对低功耗嵌入式现场可编程SoC，并在Zedboard上进行了测试。 在编写CIFAR-10测试集中的10000张图像时，错误率是11.19％。(bnn-fpga is an open-source implementation of a binarized neural network (BNN) accelerator for CIFAR-10 on FPGA. The architecture and training of the BNN is proposed by Courbarieaux et al. and open-source Python code is available. Our accelerator targets low-power embedded field-programmable SoCs and was tested on a Zedboard. At time of writing the error rate on the 10000 images in the CIFAR-10 test set is 11.19%.)
- 2020-07-27 07:02:34下载
- 积分：1
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一个精确的到0.01s的时钟源程序，对于初学VHDL理解很有帮助，只给了源程序没有给出仿真波形...
一个精确的到0.01s的时钟源程序，对于初学VHDL理解很有帮助，只给了源程序没有给出仿真波形-An accurate clock source to the 0.01s for the beginner to understand VHDL helpful not only to the simulation waveform of the source
- 2022-02-19 22:00:27下载
- 积分：1
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用VHDL语言实现的ARM处理器的标准内核的源代码程序，可在重用...
用VHDL语言实现的ARM处理器的标准内核的源代码程序，可在重用-use of the VHDL standard ARM processor core source code procedures, the reuse
- 2023-06-17 04:15:04下载
- 积分：1
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UART to send the complete procedure, including the complete source code of nucle...
UART的完整发送程序，包括完整的工程核源代码。-UART to send the complete procedure, including the complete source code of nuclear engineering.
- 2022-01-28 15:16:09下载
- 积分：1
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组合下载器SCH-3-RENEW
说明： 有自己制作的下载器原理图，包含了stlinkv2,XDS100V3,USBBLASTER.原理图和封装，一款多功能下载器。(Have their own production downloader schematic diagram, contains stlinkv2, XDS100V3, USBBLASTER. Schematic diagram and encapsulation, a multi-function downloader.)
- 2019-02-28 17:27:16下载
- 积分：1
