-
CPU-master
misp,五级流水源码,实现一个建议的cpu(Misp, five-stage flow source code, implementation of a recommended CPU)
- 2020-06-16 00:00:07下载
- 积分:1
-
arp_2
rgmii接口通讯方式,用于FPGA以太网口开发(Rgmii interface communication mode)
- 2018-11-09 21:56:27下载
- 积分:1
-
wimax_ofdm-master
wimax ofdm系统评估代码 wimax ofdm system code 很有参考价值(wimax ofdm system code)
- 2018-11-15 16:35:20下载
- 积分:1
-
用CPLD驱动扬声器实现音乐的播放,程序是用VERILOG写的,
用CPLD驱动扬声器实现音乐的播放,程序是用VERILOG写的,-CPLD driver speakers with music player, the program is written in VERILOG,
- 2022-03-20 12:37:01下载
- 积分:1
-
高科技的发展使芯片设计不再是半导体工业的领域,现场可编程逻辑阵列(FPGA)的出现使通过软件来快速实现芯片设计成为可能。本系统是广泛面向全球的工程技术人员和大专...
高科技的发展使芯片设计不再是半导体工业的领域,现场可编程逻辑阵列(FPGA)的出现使通过软件来快速实现芯片设计成为可能。本系统是广泛面向全球的工程技术人员和大专院校学生,使您能够在最短的时间内掌握FPGA的应用与VHDL/AHDL/Verilog HDL这一电子逻辑设计利器,迅速的加入高级电子设计人才行列。-The development of high-tech chip design is no longer the field of semiconductor industry, field programmable logic arrays (FPGA) through the emergence of chip design software to quickly achieve the possible. This system is a broad global engineering and technical personnel and college students, so that you can in the shortest possible period of time to master the application of FPGA and VHDL/AHDL/Verilog HDL logic design of the electronic weapon, quickly adding advanced electronic design talent ranks.
- 2023-05-14 03:35:03下载
- 积分:1
-
ISE为开发环境,Verilog语言编写程序
以ISE为开发环境,Verilog语言编写程序。功能:FPGA控制 LCD_1602动态显示秒表(In the development environment of ISE, Verilog language is used to write programs. Function: LCD_1602 dynamic display stopwatch controlled by FPGA)
- 2020-06-20 00:00:02下载
- 积分:1
-
VHDL代码登记并决定如何登记
vhdl code for register and detemines how register
works -vhdl code for register and detemines how register
works
- 2022-06-18 22:43:42下载
- 积分:1
-
gtx
ip core of the transceiver gtx
- 2019-04-02 00:10:03下载
- 积分:1
-
MAC
在FPGA硬件上,使用verilog语言编写的一个乘累加器程序。(FPGA hardware, a multiply accumulator verilog language program.)
- 2012-10-18 20:28:25下载
- 积分:1
-
prueba
Test for VHDL just a student version
- 2016-11-17 18:49:33下载
- 积分:1