-
JTAG
边界扫描技术相关资料，含各个模块的介绍。很有参考价值。(JTAG TAG CONTROLLER)
- 2016-02-24 19:10:03下载
- 积分：1
-
16 point radix 2
使用 c languageit 的 16 点基 2 fft 代码将 16 点时间域序列转换为频率域
- 2022-10-05 23:25:03下载
- 积分：1
-
telephone-cost-metering
该程序用来实现电话计时以算取费用，比较简单(telephone cost metering verilog code)
- 2013-11-03 19:45:00下载
- 积分：1
-
fpga
简易数字存储示波器verilog源代码 经过EP2C8Q208C8验证(Simple digital storage oscilloscope verilog source code has been verified EP2C8Q208C8)
- 2013-07-16 13:04:03下载
- 积分：1
-
PID_Verilog
说明： 之前一直找不到自学编写了一个，PID案例，分享下(I have been unable to find a self-taught, compiled a PID case, share under)
- 2020-10-08 13:26:54下载
- 积分：1
-
based on the nios ii drive the gpa module of altera de1 develop board,it s only...
基于NIOS驱动ALTERA DE1开发板的GPS模块工程-based on the nios ii drive the gpa module of altera de1 develop board,it s only a reference project
- 2023-08-30 05:55:06下载
- 积分：1
-
JTAG design verilog code.
JTAG design verilog code.
- 2022-02-14 02:08:42下载
- 积分：1
-
xilinx 开发板程序，LED灯控制程序
xilinx 开发板程序，LED灯控制程序-Xilinx development board procedures, LED lamp control procedures
- 2022-08-08 23:14:07下载
- 积分：1
-
一些例子程序需要的话可以下来看看新手推荐
一些例子程序需要的话可以下来看看新手推荐-Some examples of procedures can be down if necessary to see novice Recommended
- 2023-02-24 02:05:03下载
- 积分：1
-
multi16
有符号16位乘法器。经典booth编码。拓扑结构为wallance树。加法器类型是进位选择加法器。(Number system: 2 s complement
Multiplicand length: 16
Multiplier length: 16
Partial product generation: PPG with Radix-4 modified Booth recoding
Partial product accumulation: Wallace tree
Final stage addition: Carry select adder
)
- 2013-01-01 14:13:58下载
- 积分：1
