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Verilog ADPLL文件和testbench。V
verilog ADPLL file with testbench.v
- 2022-02-25 04:56:13下载
- 积分：1
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This project features a full
This project features a full-hardware sound compressor using the well known algorithm: IMA ADPCM.
The core acts as a slave WISHBONE device.
The output is perfectly compatible with any sound player with the IMA ADPCM codec (included by default in every Windows). Includes a testbench that takes an uncompressed PCM 16 bits Mono WAV file and outputs an IMA ADPCM compressed WAV file.
Compression ratio is fixed for IMA-ADPCM, being 4:1.
PLEASE NOTICE THAT THIS CORE IS LICENSED UNDER http://creativecommons.org/licenses/by-nc-sa/3.0/ (Creative Commons Attribution-Noncommercial-Share Alike 3.0 Unported). That means you may use it only for NON-COMMERCIAL purposes.
- 2022-07-25 20:05:07下载
- 积分：1
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32位二进制除法器2
- 2023-01-06 11:10:03下载
- 积分：1
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eDP
eDP接口TFT-LCD显示驱动原码（verilog+c）(eDP Interface TFT-LCD display driver source code (verilog+c))
- 2020-10-17 09:17:27下载
- 积分：1
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RapidIO_avalonst
RapidIO：使用Avalon-ST直通接口的实现方法，可以在fpga上实现(rapidio altera)
- 2017-05-31 22:50:11下载
- 积分：1
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DDC_Ver1.0
数字下变频（DDC）在如今基于软件无线电的架构中对系统的整体性能决定性的影响，代码为基于Matlab的4通道DDC程序，程序中可以根据需要调节滤波器等参数评估DDC的性能对于使用FPGA实现DDC有较大的参考价值(Digital down conversion (DDC) in today' s architecture based on software radio system a decisive impact on the overall performance of the code for the 4-channel DDC Matlab-based program, the program can be adjusted according to filter parameters such as the use of performance assessment FPGA DDC DDC has achieved great reference value)
- 2010-08-04 18:33:14下载
- 积分：1
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apbi2c_latest.tar
APB总线协议转I2C总线协议的接口IP，verilog代码实现，包含详细testbench(APB bus interface to I2C bus interface IP，verilog code )
- 2020-09-16 10:27:55下载
- 积分：1
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基于VHDL数字频率计
基于vhdl可用的数字频率计，误差较小，精准度较高。文件中还包含了与arm的通信模块、
- 2022-03-05 17:19:11下载
- 积分：1
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mig_7series_v1_9
DDR3控制器源码，针对XilinxFPGA的DDR3控制器的源码，已经验证通过。(DDR3 Controller，complete DDR3 controll，have pass verificaion.)
- 2016-08-16 09:27:43下载
- 积分：1
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程序是用硬件描述语言（VHDL）实现：4×4键…
程序主要是用硬件描述语言（VHDL）实现：
4*4键盘扫描，简洁明了，通俗易懂，比较适合VHDL初学者-procedure was used in hardware description language (VHDL) to achieve : 4* 4 keyboard scan, concise, easily understood and more suitable for beginners VHDL
- 2022-01-31 18:02:15下载
- 积分：1
