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OFDM-Verilog
基于FPGA的OFDM的实现,Verilog语言。(OFDM based on FPGA,by Verilog)
- 2021-02-03 20:59:58下载
- 积分:1
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scramble
VHDL编写加扰和解扰程序,程序连在一起仿真正确,并通过下板子抓数据验证程序没问题-Write scrambling and descrambling program, VHDL program together properly simulation, and data validation procedures is caught by the board no problem
- 2022-03-03 18:10:46下载
- 积分:1
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FPGA DDS
使用DE2实现DDS,步骤简单,配置管脚可自查看(Using DE2 to realize DDS, the steps are simple and the pins can be self-checked.)
- 2020-06-23 10:00:01下载
- 积分:1
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基于FPGA和IP核的FIR低通滤波器
用verilog语言实现数字电路低通滤波器(Implementation of digital circuit low-pass filter using Verilog language)
- 2017-10-11 10:06:40下载
- 积分:1
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marquee
Multisim11下8051跑马灯仿真。(The 8051 Marquee under Multisim11 simulation.)
- 2012-11-07 23:12:12下载
- 积分:1
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数字频率计
设计一简易数字频率计,其基本要求是:
1)测量频率范围0~999999Hz;
2)最大读数999999HZ,闸门信号的采样时间为1s;.
3)被测信号可以是正弦波、三角波和方波;
4)显示方式为6位十进制数显示;
5)具有超过量程报警功能。
5)输入信号最大幅值可扩展。
6)测量误差小于+-0.1%。
7)完成全部设计后,可使用EWB进行仿真,检测试验设计电路的正确性。(The basic requirements of designing a simple digital frequency meter are:
1) The measuring frequency range is 0-999999 Hz.
2) The maximum reading is 999999HZ, and the sampling time of gate signal is 1 s.
3) The measured signal can be sine wave, triangle wave and square wave.
4) The display mode is 6-bit decimal number display.
5) It has alarm function beyond range.
5) The maximum amplitude of input signal can be expanded.
6) The measurement error is less than +0.1%.
7) After completing all the design, EWB can be used to simulate and test the correctness of the circuit.)
- 2019-06-20 12:47:51下载
- 积分:1
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altremote_update_cyclone5
altera remote updata cyclone5 平台例程,无nios核版本(altera remote updata cyclone5 platform routine
do not use nios)
- 2021-04-23 17:38:47下载
- 积分:1
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FirlterTeam
数字滤波器组。包含matlab程序和word说明。通过一个低通数字滤波器和多个带通数字滤波器组合成一个滤波器组(Groups of the digital filter. Contains matlab program and word description. Through the combination of a low pass digital filter, and a plurality of band-pass digital filter into a filter bank)
- 2013-01-15 20:38:33下载
- 积分:1
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NIOSII-Qsys_v1.3.1
黑金刚FPGA开发板使用说明文档,讲诉了NIOS和Qsys的详细开发步奏,值得学习。(KINGBOX FPGA development board documentation, recounts in detail the development of step-outs and Qsys NIOS, it is worth learning.)
- 2015-03-25 13:42:03下载
- 积分:1
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fir
vhdl code for fir filter
- 2011-02-18 11:51:26下载
- 积分:1