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i2c
说明： 本文研究的IIC总线控制器具有如下特征
1.兼容飞利浦I2C标准，以主机模式与外围设备进行数据通信，对IIC从机模型进行读/读，读/写，写/写，写/读[18]。
2.多主操作
3.软件可编程时钟频率
4.时钟拉伸和等待状态生成
5.软件可编程确认位
6.时钟同步设计
7.仲裁中断丢失，自动转移取消
8.开始/停止/重复启动检测/确认生成
9.总线忙检测(The IIC bus controller studied in this paper has the following characteristics.
1. Compatible with Philips I2C standard, data communication between host mode and peripheral devices, read/read, read/write, write/write, write/read for IIC slave model [18].
2. Multiple Main Operations
3. Software programmable clock frequency
4. Clock stretching and waiting state generation
5. Software Programmable Confirmation Bit
6. Clock Synchronization Design
7. Loss of arbitration interruption and cancellation of automatic transfer
8. Start/Stop/Repeat Start Detection/Verification Generation
9. Bus busy detection)
- 2019-06-18 12:18:10下载
- 积分：1
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2010_5
PI控制器的算法及源码，迅速掌握FPGA的VHDL算法实现！(Algorithm and source code of PI controller, quickly grasp the implementation of VHDL algorithm in FPGA!)
- 2014-07-04 15:25:59下载
- 积分：1
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hamming
verilog语言实现一个CPU，汇编程序实现汉明编码功能，输入11位代码，输出15位编码结果。(Verilog language to achieve a CPU, assembler to achieve Hamming coding function, enter 11 bit code, output 15 bit encoding results.)
- 2020-07-03 14:00:01下载
- 积分：1
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ldpc_decoder_802_3an
802.3an ldpc码编码、译码设计，使用VERILOG hdl语言编写，包括测试代码，(802.3an ldpc code encoding, decoding the design, use of language VERILOG hdl, including test code,)
- 2021-02-14 15:29:49下载
- 积分：1
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exp8
浙江大学体系结构实验课代码 实现5级流水线带有停顿，旁路和控制竞争的处理。(Experimental Architecture, Zhejiang University course code with a pause 5-stage pipeline, bypassing the treatment and control of competition.)
- 2020-09-26 12:07:46下载
- 积分：1
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这是用VHDL实现的8位加法器，对新手有点帮助。
这是用VHDL实现的8位加法器，对新手有点帮助。-This is achieved using VHDL adder 8, a little help to novices.
- 2022-07-20 21:54:41下载
- 积分：1
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chengxu
设计制作一个可容纳4组参赛者的数字智力抢答器，每组设置一个抢答按键；
电路具有一第一抢答信号的鉴别和锁存的功能。在主持人将系统复位并发出抢答指令后，若参加者按抢答键，则该组指示灯亮并用组别显示抢答者的组别。此时，电路具有自锁功能，使别组的抢答开关不起作用。
设置计分电路。每组在开始时预置成6分，抢答后主持人计分，答对一次加1分。(The design can accommodate a the Entrants digital intellectual Responder, each set answer in a key circuit has a first answer in the signal to identify and latch functions. Host to the system reset and sent the answer in instruction, participants answer in key, the group of the group light and display the answer in the group. At this point, the circuit has a self-locking function does not work in other groups to answer switch. Set Scoring circuit. Preset six points each at the beginning of the answer in scoring after the host, answer time, add 1 point.)
- 2012-06-10 12:58:44下载
- 积分：1
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zidongmen1
控制步进电机转动，正反转，旋转角度完美掌握。很好用，亲测(Control stepping motor rotation, positive and negative rotation, perfect control of rotation angle. Very easy to use, personal test)
- 2018-12-25 16:41:07下载
- 积分：1
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Verilog_HDLjiaocheng
Verilog HDL教程
什么是Verilog HDL？
Verilog HDL 硬件描述语言(What is a Verilog HDL tutorials Verilog HDL? Verilog HDL hardware description language)
- 2009-06-15 21:44:11下载
- 积分：1
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Flash-Memory-RAM
周立功Fusion StartKit，fpga开发板的实验例程，Flash Memory初始化RAM实验(ZLG Fusion StartKit, fpga development board test routines Flash Memory Initialize RAM experiments)
- 2013-03-07 20:36:48下载
- 积分：1
