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本源码详细介绍了UART的经典实例，敬请下载，谢谢适用
本源码详细介绍了UART的经典实例，敬请下载，谢谢适用-The source described in detail a classic example of UART, please download, Thank you apply
- 2022-03-22 20:09:19下载
- 积分：1
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CCD
对ccd图像进行解码采集，并通过VGA输出(Ccd image decoding of the collection, and through the VGA output)
- 2009-07-16 22:35:30下载
- 积分：1
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信号的提取
说明： 1、SignalTap II Logic Analyzer使用方法；
2、掌握捕获条件的设置
3、学会硬件信号分析，了解硬件信号监视和软件调试的差异(1. How to use signaltap II logic analyzer;
2. Master the setting of capture conditions
3. Learn hardware signal analysis, understand the difference between hardware signal monitoring and software debugging)
- 2021-01-11 14:31:37下载
- 积分：1
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FPGA development board to write the Verilog code: function is from the client co...
FPGA开发板上写的Verilog代码：
功能是从电脑端发送一个字节，然后把它接收回来。
-FPGA development board to write the Verilog code: function is from the client computer sends a byte, and then receive it back.
- 2022-03-17 03:39:34下载
- 积分：1
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DisplayPort Link training optimization
说明： 介绍了Displayport规格中lind training的背景研究，设计和实现。(As the requirement for bandwidth continues to increase in the video market, retaining
the signal integrity becomes increasingly more difficult. For many of todays
commonly used video interfaces, there are devices that can be used to assist in this
matter. However, the use of such a device is only partially documented in the DisplayPort
specification for the receiving image device, which means that the receiving
side of the video link is free to choose its own implementation. This report presents,
together with background research and design decisions, a suggestion for such an
implementation. This implementation would need to be compatible towards a wide
range of possible video Source devices and DisplayPort cables.)
- 2021-01-11 16:48:49下载
- 积分：1
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verilog-lfsr-master
Fully parametrizable combinatorial parallel LFSR/CRC module. Implements an unrolled LFSR next state computation. Includes full MyHDL testbench.
- 2020-06-24 21:40:01下载
- 积分：1
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oc_i2c_master_top_v92
I2C IP for Quartus V9.0 sp2, can used in SOPC builder.
- 2009-10-10 10:43:18下载
- 积分：1
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Golden Week Ligong Verilog HDL reference guide, learning VerriLog things.
周立功Verilog HDL黄金参考指南，学习VerriLog的东西。-Golden Week Ligong Verilog HDL reference guide, learning VerriLog things.
- 2022-04-28 19:53:04下载
- 积分：1
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ozgul2013
说明： Digital pre-distortion (DPD) is an advanced digital
signal-processing technique that mitigates the effects of power
amplifier (PA) nonlinearity in wireless transmitters. DPD plays
a key role in providing efficient radio digital front-end (DFE)
solutions for 3G/4G basestations and beyond. Modern FPGAs
are a promising target platform for the implementation of flexible
wireless DFE solutions, including DPD.
- 2019-01-05 18:20:30下载
- 积分：1
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RANGEN
2011年全国大学生电子设计竞赛E题“简易数字信号传输性能分析仪”fpga的控制代码，verilog编写；包括了M序列及同步时钟的提取等所有程序。(2011 National Undergraduate Electronic Design Contest E title "Simple digital signal transmission performance analyzer" fpga control code, verilog prepared including the M-sequence and synchronous clock extraction and all other programs.)
- 2020-10-27 17:09:59下载
- 积分：1
