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非常多的verilog实例，对于刚入门者比较有用
非常多的verilog实例，对于刚入门者比较有用-lot of verilog example, just beginners more useful
- 2022-03-17 16:05:10下载
- 积分：1
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JTAG design verilog code.
JTAG design verilog code.
- 2022-02-14 02:08:42下载
- 积分：1
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vhdl um teste com muita coisa interessante ae pra ver
vhdl um teste com muita coisa interessante ae pra ver
- 2023-07-05 20:40:02下载
- 积分：1
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master and slave code
集成电路的规模日益扩大
- 2022-03-02 13:07:25下载
- 积分：1
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assg-9-1-(lift-controller)
Lift Controller in vhdl using process statement and state disgram
- 2013-02-28 13:42:28下载
- 积分：1
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xilinx CTC IPcore(encoder 和 decoder)的测试，经过AWGN信道。
xilinx CTC IPcore(encoder 和 decoder)的测试，经过AWGN信道。 -This simulation uses a AWGN module to include noise as part of the simulation. Prior to
running the simulation, the UniSim models for the encoder and decoder must be generated as
well as the AWGN module.
- 2022-02-03 00:45:18下载
- 积分：1
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cordic
16级流水线型cordic旋转代码以及测试文件，亲测好用(16-stage pipelined cordic rotation code and test files, pro-testing)
- 2019-03-09 08:59:01下载
- 积分：1
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clk_div3
在fpga中对于pll无法完成的分频，可采用计数方式，本例用状态机实现对时钟的奇数分频。(Pll in fpga can not be completed in the sub-frequency counting method can be used, in this case with the state machine to achieve an odd number on the clock frequency.)
- 2010-07-28 20:03:41下载
- 积分：1
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DUC
说明： 在FPGA内利用verilog实现数字上变频(apply the verilog to implement the digital up frequency)
- 2021-04-09 09:58:59下载
- 积分：1
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很好的quartus软件仿真教程，flash版。
很好的quartus软件仿真教程，flash版。-Good quartus software simulation tutorials, flash version.
- 2023-03-08 19:40:06下载
- 积分：1
