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vga
说明： 实现在屏幕上显示绿色和红色相间的水平条纹。其中，vga_640x480模块将产生行同步信号hsyn和场同步信号 vsync; vga_stripes模块将产生red、green和blue三个输出。(The horizontal stripes of green and red are displayed on the screen. Among them, vga_640x480 module will produce line synchronization signal Hsyn and field synchronization signal vsync; vga_stripes module will produce red, green and blue three outputs.)
- 2020-06-24 02:00:02下载
- 积分：1
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AT070TN83
at070tn83 800x480 tft lcd verilog 測試 quartus 文件 (800x480 tft lcd at070tn83 testing project file)
- 2020-12-07 15:39:21下载
- 积分：1
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I2C_read
说明： I2C读程序，通过状态机描叙,仿真达到要求(I2C Reading, depicts through the state machine, called Simulation)
- 2006-04-07 15:51:19下载
- 积分：1
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master_slave
说明： AXI4-Lite总线的主从机读写，例程及代码(AXI4-Lite Bus Host-Slave Read-Write, Routine and Code)
- 2019-03-22 22:24:20下载
- 积分：1
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VerilogFreq-div
Verilog分频程序原理讲解及代码.偶数倍分频奇数倍分频的原理和方法(Verilog divide the program explain the principle and code an even multiple of odd multiple of the principle of divide and divide)
- 2013-01-21 21:45:08下载
- 积分：1
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DTMB
能够完美产生数字地面电视（DTMB）的信源的程序。帧头模式为模式一。信道可选择，信号加入频偏，延时，后经滤波器后输出。(Able to produce perfect digital terrestrial television (DTMB) of the source program. Mode is the mode a header. Channels to choose from, the signal adding offset, delay, after the filter output.)
- 2013-07-25 11:22:28下载
- 积分：1
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用Matlab编写fft
在MATLAB下自编实现快速傅里叶分析，(Fast fft own procedures, faster than the system call fft slowe)
- 2020-06-23 09:00:02下载
- 积分：1
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SD_Controller_Verilog
说明： 该程序包是SD卡/MMC卡控制器SDC的verilog语言包，它包括以下4部分：RTL源代码，测试平台，软件仿真文件，说明文件。(This source package is the SD card and MMC card controler model based on the Verilog language. It has the following 4 parts: RTL language, testbench, software simulating files and help document.)
- 2021-04-05 17:39:03下载
- 积分：1
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exp12
说明： 浙江大学计算机组成实验12指令扩展多周期CPU实现(The implementation of 12 instruction extended multi cycle CPU in Computer Composition Experiment of Zhejiang University)
- 2020-10-09 16:17:35下载
- 积分：1
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52_divider
多倍（次）分频器
请注意:
本例的各个源描述的编译顺序应该是:
52_divider.vhd
52_divider_stim.vhd
(Times (times) divider Please note: This case is described in various sources to compile the order should be: 52_divider.vhd 52_divider_stim.vhd)
- 2009-09-04 09:52:18下载
- 积分：1
