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DE2_70_TV
de2 70 开发板的演示程序,verilog语言编写,视频输入输出(de2 70 development board demo program, verilog language written, video input and output)
- 2013-04-09 19:29:51下载
- 积分:1
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sdram_module3
能够实现16位的SDRAM的读写,没有仿真文件,只有SDRAM读写的源代码,用Verilog编写(can complete read or write sdram, only include Verilog code and no simulation files)
- 2013-11-25 12:43:11下载
- 积分:1
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实验12
说明: 数字逻辑实验课第十二次作业,基于Verilog的Clock时钟(Clock based on Verilog)
- 2021-03-11 15:03:46下载
- 积分:1
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ADC_Data_Recv_Module
接收机测试输入信号,
生成正余弦波,采样率、频率、幅度、相位可调节
并将生成的数据进行输出
压缩包包括Verilog代码、testbench代码、word文档
matlab仿真代码(The receiver tests the input signal,
Generation of positive cosine wave, sampling rate, frequency, amplitude, phase can be adjusted
And output the generated data
The compressed package includes the Verilog code, the testbench code
Matlab simulation code)
- 2017-12-08 17:56:02下载
- 积分:1
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A4_Uart_Top
串口! 这是一个使用的通信程序 , 非常好用。(serial port Serial port! This is a communication program used, very useful.)
- 2020-06-17 14:00:01下载
- 积分:1
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verilog
基于QUATEUS2的设计一个8位频率计verilog语言编程(The design is based QUATEUS2 an 8-bit frequency counter verilog programming language)
- 2011-12-01 20:19:48下载
- 积分:1
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基于无源蜂鸣器和矩阵按键的电子琴系统设计
基于无源蜂鸣器和矩阵按键的电子琴系统设计(design of Electronic Piano System Based on Passive Buzzer and Matrix Key)
- 2020-06-21 01:20:08下载
- 积分:1
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AD_TO_FIFO
A/D采集的数据缓存进入fifo,并通过读信号将FIFO中的数据送入网口(A/D sample data buffer to fifo,and then read enable to ethernet.)
- 2020-07-10 21:08:54下载
- 积分:1
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ppm
ppm调制的verilog代码 可实现ppm调制(ppm modulation verilog code ppm modulation)
- 2012-10-23 11:29:33下载
- 积分:1
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GPS 码 nco 码跟踪环累加模块设计
GPS code nco(GPS接收机,基带处理模块中累加模块设计代码,用于码跟踪环。代码设计巧妙,避免了消耗FPGA中比较稀缺的硬件乘法器资源)
- 2022-02-03 07:30:34下载
- 积分:1