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ANALYSIS-OF-FULL-ADDER
DESCRIPTION OF FULL ADDER
- 2013-11-12 13:32:19下载
- 积分：1
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Based on the state of the optical encoder Figure 4 multiplier vhdl procedure, en...
基于状态图的光电编码器4倍频vhdl程序，输入相位差90度的两相，输出倍频和方向信号-Based on the state of the optical encoder Figure 4 multiplier vhdl procedure, enter a 90-degree phase difference of two-phase, frequency and direction of the output signal
- 2022-03-17 02:46:02下载
- 积分：1
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tongbu
使用VERILOG开发时钟同步算法，能够从数据信号中提取时钟信息，(Clock synchronization algorithm using VERILOG developed to extract the clock from the data signal information,)
- 2020-11-11 12:39:44下载
- 积分：1
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基于ＦＰＧＡ，实现了移位除法的功能，程序接口简单，十分好用，已经验证。...
基于ＦＰＧＡ，实现了移位除法的功能，程序接口简单，十分好用，已经验证。-Based on the FPGA, to achieve the division of functional shift, the program interface is simple, very easy to use, has already been verified.
- 2022-10-14 07:10:02下载
- 积分：1
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USB接口控制器参考设计，xilinx提供的VHDL源代码
USB接口控制器参考设计，xilinx提供的VHDL源代码-USB interface controller reference design for Xilinx VHDL source code
- 2022-12-12 09:35:03下载
- 积分：1
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rmii
rmii 以太网接口时序源代码，值得开发借鉴的哦(verilog hdl)
- 2013-10-12 09:56:24下载
- 积分：1
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A simple sequential lights
A simple sequential lights
- 2022-08-17 06:37:02下载
- 积分：1
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VHDL学习手册
VHDL学习手册-VHDL study manual
- 2022-06-12 04:27:07下载
- 积分：1
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spi_controller
SPI控制器，基于VERILOG描述，分模块设计，共6个模块，时钟产生模块，移位模块，主模块，从模块，定义模块，顶层模块。(SPI controller, based on the VERILOG description, sub-module design, a total of six modules, clock generation module, shift module, main module, from the modules, custom module, top module.)
- 2021-05-13 13:30:02下载
- 积分：1
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数字频率计毕业论文 不是自己做的
数字频率计毕业论文 不是自己做的-Digital Cymometer thesis do not own. . Ha ha
- 2023-05-02 09:30:02下载
- 积分：1
