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ofdm_baseband_design_basedon_fpga
基于Xilinx FPGA的OFDM通信系统基带设计一书的源代码 (this is source code from a book)
- 2013-06-13 22:13:52下载
- 积分：1
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Analog-Digital-Wandler
关于逻辑信号的转变等等的一个程序。还包括显示(Analog-Digital-Wandler)
- 2009-11-07 20:20:28下载
- 积分：1
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6
说明： 4位数码扫描显示电路,我们控制一个七段LED需要8个输出端口；如果要输出四位十进制数，就需要32的输出端口，这将占用大量的端口资源。采用串行扫描显示，我们只需要8+4共12个端口即可。其原理是：用一个四位的输出端控制，某一时刻只选中其中的一个LED（输出为‘1’表示选中），八位的输出端将该LED所需要显示的值输出；然后四位的输出端值改变，选中下一个LED。这样依次类推。如果选择的频率很快，达到50Hz以上，由于人眼的视觉暂留效应，看起来就像4个LED同时显示。
设计一个程序，输入四个一位十进制数，用4个LED显示出来。CLK采用频率可调信号发生器，逐渐改变频率，观察扫描频率的改变对输出效果的影响。
输入：连续脉冲，逻辑开关；输出：七段LED。
(4 digital scanning display circuit, we need to control a seven-segment LED output port 8 If you want to output four decimal numbers, you need the output port 32, which will take up a lot of ports. Serial scans showed, we need only 8 of 12 ports can be+4. The principle is: the output of four with a control, a time to select only one LED (output 1 is selected), 8 output of the LED by the need to show the value of the output then The output value of the four changes, select the next LED. This and so on. If you select the frequency rapidly, reaching more than 50Hz, as the human eye s persistence of vision effect, looks like a 4 LED display simultaneously.
Design a program, enter a decimal number four, with four LED display. CLK signal generator with adjustable frequency, gradually changing the frequency of observed changes in scan frequency effect on the output.
Input: Continuous pulse, logic switches output: seven-segment LED.)
- 2010-06-21 22:07:59下载
- 积分：1
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MAX5250_Serial
说明： 对MAX5250芯片进行控制，实现DA转换输出。(Controlling MAX5250 Chip)
- 2019-06-27 14:19:36下载
- 积分：1
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串口程序 VHDL
串口程序 VHDL-Serial procedures VHDL
- 2023-02-10 04:55:04下载
- 积分：1
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fm_parcial
this is a simulation fm in simulink mathlab this is one program with pll
- 2012-11-30 10:02:10下载
- 积分：1
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用Verilog做的SD卡控制器(有详细的注释)
说明： SDIO 接口，实现SD卡的控制器功能，带有详细的注释(SDIO Interface,to realize the controller of SD Card,and have detail description.)
- 2020-06-16 22:00:01下载
- 积分：1
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LED
是一个LED点阵显示屏的原理图，非常详细，适合开发者学习(LED dot matrix display is a schematic diagram is very detailed, for developers to learn)
- 2011-11-23 00:51:02下载
- 积分：1
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FPGA实现Jpeg压缩，和视频采集程序
说明： FPGA实现Jpeg压缩，和视频采集程序(Zynq - Main - register access Mio)
- 2020-03-13 23:25:40下载
- 积分：1
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合众大公司XILINX_V4实验箱原理图
合众大公司XILINX_V4实验箱原理图-United XILINX_V4 large companies schematic experimental box
- 2022-12-12 08:15:03下载
- 积分：1
