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VHDL开发环境，四人抢答器，实现了四个人能同时抢答的功能。...
VHDL开发环境，四人抢答器，实现了四个人能同时抢答的功能。-VHDL development environment Answer four, and the realization of the four functions at the same time Answer.
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LIP4210CORE_SDIO
SDIO Verilog Sourcw code
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Verilog语言手册
Verilog Language Manual
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基于vhdl开发的频率发生器
基于vhdl开发的频率发生器-Based on the development of frequency generator vhdl
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Robotics-Toolbox-For-Matlab.tar
机器人控制,用matlab robotics toolbox 仿真设计(robotics controll using matlab robotics toolbo simulation)
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game
反应速度测试小游戏，最小外设cpld游戏，带设计说明书(Reaction speed test games, the minimum peripheral cpld game, with design specifications)
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海力士公司8M字节的SDR SDRAM实现Verilog仿真语言。
Hynix公司8M byte sdr sdram的verilog语言仿真实现。-Hynix company 8M byte sdr sdram realize the Verilog simulation language.
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TechAss-2006
un controller pi par le langage VHDL xilinx ise design 13.2
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gam7
FPGA Implementation ofLow Power 64-Point
Radix-4 FFT Processor for OFDM System
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Verilog_add_div_multi_exp
使用verilog写的32位浮点数加法模块、浮点数乘法模块、浮点数除法模块、浮点数指数模块。指数模块是综合前面三个例化成泰勒级数求指数，迭代次数（可设置）决定了精度。(Use verilog write 32-bit floating-point addition module, floating-point multiplication module, floating-point division module, the floating point number index module.Index module is a comprehensive index of the front three cases into Taylor series for calculating index, the number of iterations can be set to determine the precision)
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