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eda
EDA 正弦信号发生器：正弦信号发生器的结构有四部分组成，如图1所示。20MHZ经锁相环PLL20输出一路倍频的32MHZ片内时钟,16位计数器或分频器CNT6，6位计数器或地址发生器CN6，正弦波数据存储器data_rom。另外还需D/A0832（图中未画出）将数字信号转化为模拟信号。此设计中利用锁相环PLL20输入频率为20MHZ的时钟，输出一路分频的频率为32MHZ的片内时钟，与直接来自外部的时钟相比，这种片内时钟可以减少时钟延时和时钟变形，以减少片外干扰 还可以改善时钟的建立时间和保持时间，是系统稳定工作的保证。CNT6用来将32MHZ进行8分频得到4096HZ的频率提供给CN6与data_rom时钟信号。由CLK端输入20MHZ的时钟信号，在DOUT端就可输出稳定的正弦信号。(Sine signal generator has the structure of four parts, as shown in figure 1 below. The 20 MHZ phase lock loop PLL20 output all the way of frequency doubled within 32 MHZ slice clock, 16 counter or prescaler CNT6, six counter or address generator CN6, sine data storage data_rom. In addition to D/A0832 (shown in not draw) will digital signal into analog signals. This design using the phase lock loop PLL20 input frequency for 20 MHZ clock, the output of the frequency of all points frequency of 32 pieces (MHZ clock, and comes directly from the external clock, compared to this piece of clock can reduce the clock in delay and clock deformation, to reduce the interference of Can also improve the establishment of the clock time and keep time, is the system stability of assurance. CNT6 used to will and to 8 MHZ get 4096 HZ dividing the frequency to provide CN6 and data_rom clock signal. The input by CLK 20 MHZ clock signal, in DOUT end can output stable sine signals.
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- 2021-03-07 15:49:29下载
- 积分：1
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pci144_vhdl
PCI vhdl for Fpga designer to design PCI IP
- 2007-12-23 20:58:15下载
- 积分：1
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my
说明： 64位数据的CRC-32校验的，Verilog实现，算法并行优化(64-bit data CRC-32 checksum, Verilog implementation of a parallel optimization algorithm)
- 2011-09-17 19:36:16下载
- 积分：1
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Dual-Mode-Dual-Band-Filters
本文介绍一种波导双模双带滤波器的设计方法。(This paper presents a new class of dual-mode dualband
filters in which each polarization is dedicated to a selected
band. The equivalent circuit is a parallel combination of two inline
networks that represent each polarization. A transmission zero is
generated between the two bands by properly adjusting the relative
orientations of the input and output coupling apertures.)
- 2013-03-12 18:08:33下载
- 积分：1
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matlab
matlab file for image contrast..
- 2010-08-18 03:02:21下载
- 积分：1
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DIATAL_MATLAB_FPGA_AlteraVerilog
[数字通信同步技术的MATLAB与FPGA实现——AlteraVerilog版]书中资源代码，非常好，分享，
希望大家下下！( U651 u0B3 u09108 u09108 u0103 u0101 u7801 uFF0C u975E u5HR U597D uFF0C u5206 u4EAB uFF0C u5E0C u671B u5927 u5BB6 u4E0B u4E0B uFF01)
- 2017-05-11 13:47:58下载
- 积分：1
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Electronic organ program design implementation and simulation of vhdl source cod...
电子琴程序设计与仿真的vhdl实现的源代码-Electronic organ program design implementation and simulation of vhdl source code
- 2022-02-02 22:03:59下载
- 积分：1
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- 2022-06-02 03:55:25下载
- 积分：1
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110819_1
基于sopc的lcd时钟，开发工具为nios ii和quartus ii9.0(Based on sopc the lcd clock, development tools for the nios ii and quartus ii9.0)
- 2011-08-22 10:28:50下载
- 积分：1
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EP2C70F896C6N-pins
将VHDL程序下载到DE2开发板，引脚分配时需要知道的芯片每个引脚功能(VHDL program will be downloaded to the DE2 development board, you need to know when the pin assignments for each pin of the chip functions)
- 2020-12-09 11:09:21下载
- 积分：1
