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说明: 用VHDL语言实现电子钟(Using VHDL language electronic bell)
- 2008-11-28 21:20:23下载
- 积分:1
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velocity_Verilog
速度表(velocity)要求:1.显示汽车Km/h数;2.车轮每转一圈,有一传感脉冲;每个脉冲代表1m的距离;3.采样周期设为10s;
4.要求显示到小数点后边两位;5.用数码管显示;6. 最高时速小于300Km/h。(约为83.3m/s)
(use verilog to realize velocity)
- 2020-07-13 15:08:51下载
- 积分:1
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my_test_rw_pack9
基于Verilog HDL的SDRAM控制器。
实验条件:
工具:Quartus II 6.0 ,SignalTap II
FPGA:Altera Cyclone EP1C12Q240C8N
SDRAM:HY57V283220T-6(SDRAM controller based on Verilog HDL.
Experimental conditions:
Tools: Quartus II 6.0, SignalTap II
FPGA: Altera Cyclone EP1C12Q240C8N
SDRAM: HY57V283220T-6)
- 2013-01-31 11:13:26下载
- 积分:1
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merry-go-round
能够成功的实现走马灯功能,使LED循环亮灭(To succeed the implementation of the version function, make the LED circular light out)
- 2013-06-13 22:45:50下载
- 积分:1
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jiaotongdeng
十字路口交通灯的单片机控制源代码 红黄绿三灯 还有数码管时间显示(Intersection traffic lights SCM source code red yellow three lights and LED time display)
- 2011-08-07 23:34:04下载
- 积分:1
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RISC-V-Reader-Chinese-v2p1
RISC-V 芯片设计规范,很有参考价值,开源芯片设计必备参考资料,希望对大家有帮助。(The RISC-V Foundation is chartered to standardize and promote the open RISC-V instruction set architecture)
- 2020-07-01 23:00:02下载
- 积分:1
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DE2_Default
基于DE2开发板的VGA显示模块,仅供大家参考(DE2 development board based on the VGA display module, for your reference)
- 2008-07-21 16:12:32下载
- 积分:1
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32位-33M 从模式(target)PCI接口参考设计_lattice
说明: 32位/33M 从模式(target)PCI接口参考设计,Lattice提供。由于PCI时序较复杂,此设计仅能供参考(32/route from the model (target) PCI reference design, Lattice provided. Because PCI timing more complicated, and the design for reference only)
- 2005-10-24 19:35:04下载
- 积分:1
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串行至并行转换器 UVM 代码
UVM 基于与教程有关的验证平台的体系结构中的所有组件的验证代码。最好的入手 UVM 的家伙
- 2022-07-10 05:49:00下载
- 积分:1
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Chebyshev-filter
利用matlab设计了一个切比雪夫滤波器,并且对滤波器性能进行了仿真分析。(Using the matlab design a chebyshev filter, and has carried on the simulation analysis on filter performance.
)
- 2013-09-05 20:04:36下载
- 积分:1