-
52_divider
多倍（次）分频器
请注意:
本例的各个源描述的编译顺序应该是:
52_divider.vhd
52_divider_stim.vhd
(Times (times) divider Please note: This case is described in various sources to compile the order should be: 52_divider.vhd 52_divider_stim.vhd)
- 2009-09-04 09:52:18下载
- 积分：1
-
FPGA
Verilog学习例程EP2C5，内有跑马灯等18个程序(Verilog learning routines EP2C5, marquees and other 18 programs)
- 2020-12-06 22:29:21下载
- 积分：1
-
61EDA_B95
开发板原理图 自己可以设计开发板为什么一定要买呢(Development board schematic can design their own development board why they must buy it)
- 2008-12-09 15:58:55下载
- 积分：1
-
fir
该程序实现了一个FIR滤波加速器，该程序在FPGA板上开发，通过使用VHDL语言来定义RS232端口的使用(design a FIR Filter Accelerator based on FPGA board and RS232 interface using VHDL language. )
- 2013-06-07 06:27:32下载
- 积分：1
-
FPGA TRACKING SYS
下采样与灰度
- 2022-08-09 07:51:24下载
- 积分：1
-
用verilog写的很好的cpu core
用verilog写的很好的cpu core-using Verilog write a good cpu core
- 2023-06-03 16:40:03下载
- 积分：1
-
vhdl经典源代码――LCD控制，入门者必须掌握
vhdl经典源代码――LCD控制，入门者必须掌握-vhdl classical source code-- LCD control, beginners must master
- 2022-03-20 08:17:37下载
- 积分：1
-
卡内基梅陇大学verilog课程讲义-unlocked
说明： verilog讲义
卡内基梅陇大学verilog课程讲义-unlocked
卡内基梅陇大学verilog课程讲义-unlocked(Verilog Course Lectures at Carnegie Mellon, University Verilog Course Lectures at Carnegie Mellon University Verilog Course Lectures at Carnegie Mellon University)
- 2020-06-20 18:00:02下载
- 积分：1
-
基于fpga和xinlinx ise 的7段码led显示程序，希望对你有所帮助
基于fpga和xinlinx ise 的7段码led显示程序，希望对你有所帮助-and ideally xinlinx 7 of the code led display program, and I hope to help you
- 2022-02-03 23:57:12下载
- 积分：1
-
AGC
The AGC is a smart programmable gain amplifier (PGA). The amplifier gain is adjusted based upon
the input signal level so that the output is at a specified Target Gain. The AGC can be configured to
be either a mono or stereo input / output component. For illustration purposes, the following
discussion will highlight the stereo configuration.
- 2017-12-01 17:26:59下载
- 积分：1
