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TLC7528
fpga驱动TLC7528程序，相当好用，绝对能用(FPGA PROGRAM OF TLC7528)
- 2011-08-17 15:19:03下载
- 积分：1
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eda
EDA 正弦信号发生器：正弦信号发生器的结构有四部分组成，如图1所示。20MHZ经锁相环PLL20输出一路倍频的32MHZ片内时钟,16位计数器或分频器CNT6，6位计数器或地址发生器CN6，正弦波数据存储器data_rom。另外还需D/A0832（图中未画出）将数字信号转化为模拟信号。此设计中利用锁相环PLL20输入频率为20MHZ的时钟，输出一路分频的频率为32MHZ的片内时钟，与直接来自外部的时钟相比，这种片内时钟可以减少时钟延时和时钟变形，以减少片外干扰 还可以改善时钟的建立时间和保持时间，是系统稳定工作的保证。CNT6用来将32MHZ进行8分频得到4096HZ的频率提供给CN6与data_rom时钟信号。由CLK端输入20MHZ的时钟信号，在DOUT端就可输出稳定的正弦信号。(Sine signal generator has the structure of four parts, as shown in figure 1 below. The 20 MHZ phase lock loop PLL20 output all the way of frequency doubled within 32 MHZ slice clock, 16 counter or prescaler CNT6, six counter or address generator CN6, sine data storage data_rom. In addition to D/A0832 (shown in not draw) will digital signal into analog signals. This design using the phase lock loop PLL20 input frequency for 20 MHZ clock, the output of the frequency of all points frequency of 32 pieces (MHZ clock, and comes directly from the external clock, compared to this piece of clock can reduce the clock in delay and clock deformation, to reduce the interference of Can also improve the establishment of the clock time and keep time, is the system stability of assurance. CNT6 used to will and to 8 MHZ get 4096 HZ dividing the frequency to provide CN6 and data_rom clock signal. The input by CLK 20 MHZ clock signal, in DOUT end can output stable sine signals.
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- 2021-03-07 15:49:29下载
- 积分：1
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FIR滤波器的VHDL语言实现
FIR滤波器的VHDL语言实现-The implement of FIR Filter based on VHDL
- 2022-01-24 13:17:20下载
- 积分：1
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YCbCr444_YCbCr422
FPGA YCbCr444转YCbCr422实验 很好的参考(FPGA EP4CE40F23C6 YCbCr444 turn YCbCr422 experiment)
- 2021-01-25 10:08:38下载
- 积分：1
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based-on-fpga
基于fpga的电子血压计。pdf文档，好用，内容清楚简单，转载而来(Electronic sphygmomanometer based on fpga)
- 2013-12-05 10:57:22下载
- 积分：1
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liyuanlnx_dynamic_led
FPGA数码管显示秒表实验
三种方法实现：
方法一： 对秒计数，得到（秒显示）0~9，
对（秒显示）计数，得到（分秒显示）0~5，
对（分秒显示）计数，得到（分钟显示）0~5，
注意进位时机
方法二： 对秒计数，得到（秒显示）0~9
对秒计数，得到（分秒显示）0~5
对秒计数，得到（分钟显示）0~5
方法三：
只对秒计数，分别取模
%60得到分钟显示 ************************
余数%10得到分秒显示 （据说）取模运算占资源！！！！（也能接受？好像...）
再剩下的余数为秒显示 ************************(Experiment of Digital Tube Display Stopwatch Based on FPGA
Three ways to achieve)
- 2020-06-22 04:40:02下载
- 积分：1
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并串转换模块，内含有另个.vhd文件。一个是自己写的比较简单 另一个是参考的。...
并串转换模块，内含有另个.vhd文件。一个是自己写的比较简单 另一个是参考的。-And the string conversion module, which contains another one. Vhd file. One is its relatively simple to write the other is the reference.
- 2022-01-25 21:05:32下载
- 积分：1
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The_Ten_Commands_of_Excellent_Design
介绍了FPGA设计的十大准则，对初学者很有用，对于工作多年的同志，也会有整理总结的好处(Describes the FPGA design of the top ten criteria are useful for beginners, for many years comrades, there will be finishing the benefits of the summary)
- 2009-09-26 16:44:29下载
- 积分：1
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RC6-block-cipher-using-VHDL
VHDL implementation of RC6 encryption algorithm
Test file represent applying all zero input and all zero key
note that result is correct but bytes positions are swapped
- 2020-12-01 22:09:26下载
- 积分：1
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turbo[1].tar
turbo码的verilog程序，有意者请下载。(turbo code verilog procedures Interested parties please download.)
- 2021-01-14 17:58:46下载
- 积分：1
