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EMI
说明： Simetrix EMI滤波器设计，实际测试有效果。(Simetrix EMI filter design, the actual test results are effective.)
- 2019-10-01 22:28:37下载
- 积分：1
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progconterful
four bit counter verlog source code for veriwell including test bench
- 2010-03-29 18:54:45下载
- 积分：1
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canny
说明： canny 边缘检测基于梯度直方图的自适应阈值verilog实现(Canny edge detection based on gradient histogram adaptive threshold Verilog implementation)
- 2021-04-12 14:48:57下载
- 积分：1
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乐曲播放器
用vhdl语言编写的程序，可以播放乐曲，有分频模块，可播放梁祝等歌曲。
- 2022-01-21 18:49:47下载
- 积分：1
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Dec_mul
时间同步后即可确定每帧数据的起始位置，这样就能完整的截取下每一帧。但是，数据中还带有频偏信息。在常规的通信系统中，多普勒很小仅仅会带来很小的频偏，但是在大多普勒的情况下，频偏将非常大，20马赫的速度将会带来将近34K的频偏。因此，如何很好的纠正频偏即为本系统的难点。
OFDM中，我们将大于子载波间隔倍数的频偏称为整数倍频偏，而将小于一个子载波间隔的频偏称为小数倍频偏。频偏矫正精度只要能保证小于十分之一倍的子载波间隔，频偏就不会对均衡和解调造成影响。本文中我们借鉴这种思想，由于硬件资源限制，我们将在接收端做64点FFT，即相当于将频域划分为64份，我们将小于 的频偏称为小数倍频偏，将 整数倍的频偏称为整数倍频偏。本程序即基于SCHIMDL经典方法完成小数倍频偏纠正(After time synchronization can determine the starting position of each frame data, so you can complete the interception of each frame. However, in the data with frequency information. In conventional communication systems, doppler small will bring only small deviation, but in the case of most of the doppler, frequency PianJiang is very large, 20 Mach speed will lead to deviation of nearly 34 k. Therefore, how to good to correct deviation is the difficulty of this system.
OFDM, we will be bigger than the sub-carrier spacing ratio of frequency deviation is called the integer frequency offset, and the interval will be less than a child carrier frequency offset is called decimal frequency doubling. Deviation is less than one over ten times as long as can guarantee accuracy of sub-carrier spacing, deviation will not affect balance and demodulation. This article, we draw lessons from the idea, due to the limited hardware resources, we will do 64 points FFT at the receiving end, which is equ)
- 2013-12-26 18:00:24下载
- 积分：1
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ffirr_166i
fir低通滤波器 用于dspbuilder pll：25nss data 400khz sin 10.8khz 已通过测试。
(fir low pass filter for dspbuilder pll: 25nss data 400khz sin 10.8khz has been tested.)
- 2012-06-10 17:54:50下载
- 积分：1
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用于测试ACEX1k30的流水灯程序，晶振频率为20mhz。运行环境Maxplus2...
用于测试ACEX1k30的流水灯程序，晶振频率为20mhz。运行环境Maxplus2-for testing the water ACEX1k30 lights procedures, the frequency of 20MHz crystal oscillator. Operating environment FLEX10K
- 2023-03-02 14:05:03下载
- 积分：1
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程序采用VHDL：频率合成DDS主要调用LPM，
程序用VHDL实现：
频率合成，DDS
主要调用LPM-procedures using VHDL : frequency synthesis, DDS major call LPM
- 2023-07-07 03:20:03下载
- 积分：1
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全部通过，是我的精心设计，完全满足初学者的要求。
全部通过，是我的精心设计，完全满足初学者的要求。-all passed, I was carefully designed, fully meet the requirements of beginners.
- 2022-05-29 23:49:35下载
- 积分：1
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VGA altera detailed description of the official routine Verilog code for a very...
详细介绍了VGA官方例程Verilog代码，非常好很实用
- 2022-08-21 17:43:09下载
- 积分：1
