AES IP core

代码说明：

While there are many AES cores around, this one is designed with LUT6 based FPGA architecture in mind from day one.  The AES Decryption Core for FPGA implements the decryption portion of the AES (a.k.a. Rijndael) algorithm described in the FIPS-197 specification. Key lengths of 128 / 192 / 256 bits are supported, each with a separate instantiation wrapper. Since the core is designed to take advantage of LUT6 based FPGA archit