-
fadd16
实验用16位全加器的VHDL代码,适合初学者学习,数电学习的好工具。
(Experiment with 16-bit full adder VHDL code for beginners to learn, a good tool to learn a few power.)
- 2010-05-11 20:37:34下载
- 积分:1
-
tpc_vhd
完整的TPC编译码VHDL程序,直接就可以运行(TPC encoder and decoder)
- 2020-11-21 15:29:36下载
- 积分:1
-
Modulator70
个人参与的某国家工程并行排序MATLAB程序,用于FPGA的RTLAB仿真,使用Simulink工具生成HDL代码。测试可用。(Individuals involved in sort of a national engineering parallel MATLAB programs for the FPGA RTLAB simulation, using the Simulink tool to generate HDL code. Test available.)
- 2011-07-29 15:16:30下载
- 积分:1
-
UART1
可直接用于zedboard上的串口通信,利用zynq7000的pl部分实现一个简单的UART串口通信(Can be used directly on the zedboard serial communication, the use of zynq7000 PL part of the realization of a simple UART serial communication)
- 2020-08-14 15:18:26下载
- 积分:1
-
MAX48_cn
MAX481、MAX483、MAX485、MAX487-MAX491以及
MAX1487是用于RS-485与RS-422通信的低功耗收发器,
每个器件中都具有一个驱动器和一个接收器(The MAX481, MAX483, MAX485 The MAX487-MAX491, and MAX1487 low-power transceivers for RS-485 and RS-422 communication, each device has a drive and a receiver)
- 2012-07-10 21:28:46下载
- 积分:1
-
convotion_decode
用verilog写的卷积码的编码程序以及viterbi译码程序(Use verilog write convolution code coding procedures and viterbi decoding program)
- 2012-09-06 20:24:55下载
- 积分:1
-
FCFS_PROJECT_A
FCFS (First Come First Served) with Database
- 2014-10-09 20:23:32下载
- 积分:1
-
ddr3_sun
使用DDR3IP核进行仿真,写入读取数据(Using DDR3IP core to simulate, write and read data)
- 2021-01-07 00:48:53下载
- 积分:1
-
007
给大家上传一本非常好的关于verilog-hdl的电子书,实用,易懂,易学。此为第七章(Give us a very good upload on verilog-hdl of e-books, practical, easy-to-understand, easy to learn. This is the Chapter VII)
- 2008-04-22 16:53:33下载
- 积分:1
-
使用H57V2562GTR实现的SDRAM代码
使用verilog语言编写的SDRAM读写程序,设置为突发读、突发写、全页读写模式。
- 2022-09-07 23:15:07下载
- 积分:1