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exp_rom
通过MATLAB产生单脉冲信号的数据，存储下来作为verilog代码实现的DDS的数据源，用于验证DA数据的ddio的调试是否有问题。(The data of monopulse signal generated by MATLAB is stored as the data source of DDS implemented by Verilog code to verify whether the ddio debugging of DA data is problematic.)
- 2020-06-23 04:40:02下载
- 积分：1
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FCFS_PROJECT_A
FCFS (First Come First Served) with Database
- 2014-10-09 20:23:32下载
- 积分：1
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蓝牙HCI―UART与并口的FPGA控制接口设计
蓝牙HCI―UART与并口的FPGA控制接口设计-Bluetooth HCI-UART and parallel port control interface of the FPGA design
- 2022-07-10 22:33:51下载
- 积分：1
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VGA
verilog vga 图像处理(verilog vga)
- 2013-10-15 19:00:16下载
- 积分：1
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Quartus a complete design examples, examples from installation to completion, th...
quartus一个完整的设计例子,从安装到实例完成，仿真等全过程，适合从0开始的初学者-Quartus a complete design examples, examples from installation to completion, the entire process of simulation, etc., suitable for the beginner to start from 0
- 2022-07-26 09:40:40下载
- 积分：1
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cos
原创：cos函数和sin函数的VHDL实现，很实用(cos of the VHDL implementation)
- 2020-11-27 22:29:30下载
- 积分：1
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Synopsys使用基本步骤使用的集成工具，有用的好东西
使用synopsys的基本步骤，综合工具的使用说明，有用的好东西-Synopsys using the basic steps to use the integrated tools, useful good things
- 2022-04-06 15:39:11下载
- 积分：1
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ALTERA NIOS处理器实验，编程环境是QUARTUS，在NIOS SHELL下编译实现功能。实验USB接口...
ALTERA NIOS处理器实验，编程环境是QUARTUS，在NIOS SHELL下编译实现功能。实验USB接口-Altera NIOS processor experiments, programming environment is QUARTUS in NIOS SHELL compiler functionality. Experimental USB interface
- 2022-05-25 15:09:52下载
- 积分：1
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AD7991_7995_7999
AD7991_7995_7999转换器说明(4-Channel, 12-/10-/8-Bit ADC with
I2C-Compatible Interface in 8-Lead SOT-23)
- 2013-05-15 20:14:11下载
- 积分：1
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ahb2wishbone_latest.tar
AHB to Wishbone memory interface VHDL source code
- 2013-01-11 11:17:03下载
- 积分：1
