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dct01
Verilog编写的串口通讯下解码状态机(Verilog serial communication prepared under the decoder state machine)
- 2011-01-17 02:40:41下载
- 积分:1
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为了便于信号发射,提高信道利用率、发射功率效率以及改善通信质量,人们研制出各种通信信号的调制样式。尽管调制样式多种多样,但实质上调制不外乎用调制信号去控制载波的...
为了便于信号发射,提高信道利用率、发射功率效率以及改善通信质量,人们研制出各种通信信号的调制样式。尽管调制样式多种多样,但实质上调制不外乎用调制信号去控制载波的某一个(或几个)参数,使这个参数按照调制信号的规律而变化。调制信号可以分别“寄生”在已调信号的振幅、频率和相位中,相应的调制就是调幅、调频和调相这三大类熟知的调制方式。
MSK信号就是调频这一大类中的一种相位连续的移频键控。其主要特点是包络恒定,带外辐射小,实现较简单,可用于移动通信中的数字传输
-see up
- 2022-06-26 02:16:48下载
- 积分:1
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smartWasher
QUARTER编程环境实现的智能洗衣机系统,通过DE0板子进行模拟,组要完成洗衣机5个步骤的顺序过程以及系统相应动作(QUARTER programming environment of intelligent washing system, through simulation DE0 board, groups 5 to complete the washing process and the system the sequence of steps corresponding action)
- 2020-11-06 13:19:49下载
- 积分:1
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verilog-learning-of-HuaWei
华为公司学习verilog的资料,绝密资料,想学习verilog编程,想学习FPGA,想以后进华为公司的都可以看看。(Huawei learning verilog information, confidential information, want to learn verilog programming, want to learn FPGA, think later into the Huawei can see.)
- 2013-07-23 14:48:30下载
- 积分:1
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一种基于格雷码的异步FIFO设计与实现,8*8位的fifo VHDL 源码
一种基于格雷码的异步FIFO设计与实现,8*8位的fifo VHDL 源码-Gray-code based on the Asynchronous FIFO Design and Implementation
- 2022-08-23 15:10:52下载
- 积分:1
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verilog-lfsr-master
Fully parametrizable combinatorial parallel LFSR/CRC module. Implements an unrolled LFSR next state computation. Includes full MyHDL testbench.
- 2020-06-24 21:40:01下载
- 积分:1
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DDS
文利用直接数字频率合成器(DDS)与CPLD技术和单片机控制技术,研制和
设计了高分辨率、高稳定度的函数信号发生(Wen using direct digital frequency synthesizer (DDS) and CPLD technology and single-chip microcomputer control technology, development and
Design of high resolution, high stability function of the signal
)
- 2013-08-27 14:20:22下载
- 积分:1
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VGA_Display(FPGA)
在FPGA开发平台上,通过按键控制一个弹球小游戏。输出VGA显示信号输送到显示器上显示(On the FPGA development platform button control of a pinball game. VGA output signal is supplied to the display displayed on the display)
- 2017-05-02 10:59:42下载
- 积分:1
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EDanDanAssistg
蛋蛋助手,可以动态配置生成代码格式,方便ORM或或程序员的生成工作 ,经测试
(Egg assistant, can be dynamically configured to generate code format, convenient ORM, or programmer generation work, tested)
- 2012-09-10 00:33:07下载
- 积分:1
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imply logic
说明: 由忆阻器机制设计蕴含逻辑,内含testbench仿真文件(Design implied logic by memristor mechanism, including testbench simulation file)
- 2019-04-24 15:42:24下载
- 积分:1