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CY7C68013A_board_test
该资料基于FPGA实现USB2.0的高速传输，即CY7C68013A芯片的数据传输，包括FPGA与上位机之间数据的相互传输，CY7C68013A的传输速率最高可达480M/S。(The FPGA-based high-speed data transmission USB2.0, that CY7C68013A chip data transmission, including the mutual transmission of data between the FPGA and the host machine CY7C68013A transfer rate up to 480M/S.)
- 2020-08-24 21:48:15下载
- 积分：1
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30
说明： 30 bus for atp design
- 2016-02-14 19:41:55下载
- 积分：1
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spwm
关于SPWM调制设计VHDL代码
关于SPWM调制设计VHDL代码(SPWM modulation on the design of VHDL code design on the VHDL code modulation SPWM)
- 2021-03-16 09:19:22下载
- 积分：1
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2MW_wind_grid_inverter
针对兆瓦级风电并网逆变器主电路研制中存在的并联扩容、开关频率较低和LCL滤波器难以优化设计等问题，提出了采用交流侧串接电感再进行并联的均流方案，采用载波移相技术提高变流器的等效开关频率，提出了LCL滤波器的设计原则，并给出了上述设计的理论依据和实现方法。通过对2兆瓦风电变流器主电路的仿真验证了上述技术方案。(MW-class wind power for grid-inverter main circuit of the parallel development of existing capacity, a lower switching frequency and LCL filter design difficult to optimize the problem, a series inductor AC side in parallel are further flow program, the use of carrier phase-shifting technology to enhance the equivalent converter switching frequency, a LCL filter design principles, and gives the above-mentioned theoretical basis for the design and implementation. 2 MW of wind power converter main circuit simulation program to verify the above-mentioned technology.)
- 2009-04-28 09:16:38下载
- 积分：1
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GPS/BD开源原代码，verilog 有很强的借鉴意义
verilog编写的GPS /BD基带逻辑代码，包含跟踪相关部分代码，有比较好的借鉴意义。
- 2022-03-11 22:42:41下载
- 积分：1
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FPGA_SOURCE_CODE
ad9910 FPGA VERILOG 初始化代码，(Ad9910 FPGA VERILOG initialization code)
- 2017-08-01 10:01:28下载
- 积分：1
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fir_verilog_matlab
本设计是基于FPGA的一个FIR低通滤波器设计，要求使用Verilog语言编写滤波器模块，通过编译和综合，并通过Matlab和modelsim联合仿真验证设计结果。(This design is a FIR low-pass filter design based on FPGA, use Verilog to program filter module, and joint simulation by Matlab and modelsim to validate the design results.)
- 2014-03-21 09:58:41下载
- 积分：1
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fifo
说明： 用FPGA完成256*8的存储器的读写操作( complete reading and writing 256* 8 memory with FPGA )
- 2010-04-24 17:07:06下载
- 积分：1
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Tym605V2Demo
FPGA（赛灵思）试验箱 实验程序 有Audio,Buzzer,key,ledarray,ledseg.......(FPGA（赛灵思）试验箱 实验程序Audio,Buzzer,key,ledarray,ledseg)
- 2012-02-11 21:09:19下载
- 积分：1
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3he11
产生SH,SP,RS,SP,φ1,φ2驱动脉冲，用于驱动TCD1501的的源代码(To generate SH, SP, RS, SP, φ1, φ2 drive pulse for driving TCD1501 source code)
- 2013-05-15 20:50:30下载
- 积分：1
