登录
首页 » VHDL » 适用于FPGA的SOPC方面的元器件添加,如COMPNENT

适用于FPGA的SOPC方面的元器件添加,如COMPNENT

于 2022-02-10 发布 文件大小:365.54 kB
0 122
下载积分: 2 下载次数: 1

代码说明:

适用于FPGA的SOPC方面的元器件添加,如COMPNENT-Applicable to FPGA-SOPC area to add components, such as COMPNENT

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • DS18B20
    DS18B20温度传感器的基于FPGA的编程通信,使用VHDL语言(DS18B20 temperature sensor based FPGA programming communication with VHDL)
    2012-07-16 19:10:29下载
    积分:1
  • 加减法器
    可实现两个4bit补码的加法及减法,有溢出提示(adder with overflow hint)
    2017-07-19 20:52:42下载
    积分:1
  • 用Verilog HDL语言编写的AT24C04程序,并用数码管显示,已经过测试,很好用...
    用Verilog HDL语言编写的AT24C04程序,并用数码管显示,已经过测试,很好用-With the Verilog HDL language of the AT24C04 procedures and use digital tube display, has been tested, very good to use--
    2022-03-19 15:00:00下载
    积分:1
  • CodedLOCK
    基于FPGA的电子密码锁设计与实现,语言是VHDL语言,有注释(FPGA-based design and implementation of electronic locks, language is VHDL language, annotated)
    2013-08-27 21:37:06下载
    积分:1
  • processor
    processor design istruction load pipeline ,hazard
    2010-04-02 03:52:08下载
    积分:1
  • 10。对于密钥输入一个密码锁,假设重置后的七个香格里拉…
    10对于进入密码锁的按键,假设复位后七个灯显示0,使用sw1、sw2两个键输入,只要按sw1键,并使七个灯显示每秒速度加1的值,但释放sw1键后停止。
    2023-01-16 19:45:03下载
    积分:1
  • 用verilog实现FSK调制,称为IP核来实现模块…
    用Verilog实现FSK调制,调用IP核实现正弦余弦的调制-Verilog implementation using FSK modulation, called IP core to achieve the modulation sine cosine
    2022-03-15 17:40:05下载
    积分:1
  • VHDL_count 从 0000 到 9999 7 段 LED 显示器 (đếm 慈 0000 đến 9999 hiển 施耐 4 领导 7 đoạn)
    VHDL_count 从 0000 到 9999 7 段 LED 显示器 (đếm 慈 0000 đến 9999 hiển 施耐 4 领导 7 đoạn)
    2022-02-24 20:50:42下载
    积分:1
  • DDR SDRAM控制器verilog代码及中文说明文档,对DDR开发很有用的哈。...
    DDR SDRAM控制器verilog代码及中文说明文档,对DDR开发很有用的哈。-Verilog source code for DDR SDRAM controler design,including guide book in chinese.
    2022-03-10 08:09:15下载
    积分:1
  • TOFED_TB_1
    A 4 bit twisted ring counter is a sequential circuit which produces the following sequence of output values: 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001 and then repeats. Design a circuit for a 4 bit twisted ring counter that uses four D flip flops. Draw a state transition diagram, a state table and a schematic for your circuit. Design an alternate implementation using just three flip flops and draw a state transition diagram, state table and a schematic for your circuit. If your designs are extended to implement an n bit twisted ring counter, how many flip flops are required using each of the two approaches. In what situations would you prefer the first method? In what situations would you prefer the second?
    2014-11-08 06:58:55下载
    积分:1
  • 696518资源总数
  • 106242会员总数
  • 10今日下载