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altera de2 sd 卡源程序。调试成功的
altera de2 sd 卡源程序。调试成功的-altera de2 sd card source. Debugging success
- 2022-06-20 23:18:53下载
- 积分：1
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4ASKmod2
讲述4ASK的原理并附有matlab调制解调的源码。。。。。。。。。。
注：原来上传的4ASKmod.zip不要下(The principle tells 4ASK together with modulation and demodulation matlab source. . . . . . . . . . Note: The original upload 4ASKmod.zip not down)
- 2013-07-10 00:01:10下载
- 积分：1
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jiaozhijiejiaozhi
VHDL代码完成行列交织与解交织的功能实现(the realization of interleaver on VHDL language)
- 2020-07-17 15:08:49下载
- 积分：1
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recarry
fir filter 程序
老师上课留的作业，在这里跟大家分享一下，希望能有所帮助(fir filter procedures teacher in the class to stay the operation here to share with you, hope can be helped)
- 2006-10-11 19:34:43下载
- 积分：1
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license
quartus license dede(quartus 11.0 license)
- 2014-04-21 18:26:12下载
- 积分：1
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turbo_dinter
说明： 电网协议信道解交织器设计FPGA实现，适用于PB16的宽带电力线载波通信(Grid protocol channel deinterleaver design FPGA implementation, suitable for PB16 broadband power line carrier communication)
- 2020-05-08 15:53:18下载
- 积分：1
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gobang
一个用verilog实现的五子棋程序，用在fpga上，连接显示器，可选择与电脑对战或是双人对战，按wsad控制方向，回车控制落子，程序会自动判断输赢并显示结果(A 331 procedures implemented by verilog, used in fpga, connect the monitor, you can choose to play against the computer or a double play, press wsad control the direction, carriage control Lazi, the program will automatically determine the winners and losers and display the results)
- 2015-03-30 13:13:35下载
- 积分：1
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veilog code user can derict use it for the base mode.
veilog 代码 用户可以直接调用，作为底层模块。同时已经编译成功，可以作为基本单元库。-veilog code user can derict use it for the base mode.
- 2023-08-09 02:40:03下载
- 积分：1
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bt656_to_yuv422
从bt656数据流中提取出同步信号, 适合于搞fpga/cpld开发调式(bt656 internel sync to extern sync singal，
bt656 internel sync to extern sync singal)
- 2021-03-06 11:19:30下载
- 积分：1
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shiyan5
应用布莱克曼窗实现FIR滤波器，并绘制相应波形图案(Application Blackman window FIR filter, and draw the corresponding waveform pattern)
- 2014-01-09 11:50:49下载
- 积分：1
