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印制线路板设计经验点滴
印制线路板设计经验点滴-Printed Circuit Board Design Experience
- 2022-04-09 19:37:37下载
- 积分：1
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DDs直接数字频率合成器的源代码，其中包括采用IP核和普通两种方式...
DDs直接数字频率合成器的源代码，其中包括采用IP核和普通两种方式-DDS Direct Digital Synthesizer source code, including the use of IP core and the general two ways
- 2022-01-23 11:02:21下载
- 积分：1
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ofdm_modulation
OFDM modulation source code written in Matlab
- 2009-06-01 17:52:44下载
- 积分：1
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hdb3_codedecode
说明： 用VERILOG实现的，hdb3编码器和解码器，经过前仿真和后仿真成功(Achieved with the VERILOG, hdb3 encoder and decoder, after a successful pre-simulation and post simulation)
- 2021-04-22 15:58:49下载
- 积分：1
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shperedecode
基于软输出固定复杂度球形译码的高效迭代检测算法，最新的球形译码论文(Iterative detection algorithm based on a fixed complexity soft-output sphere decoding efficiency, sphere decoding papers)
- 2012-09-07 20:36:21下载
- 积分：1
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szdyb
关于数字电压表的vhdl实现，有仿真程序，可以下载到板子中。(Vhdl digital voltage meter on the implementation of a simulation program can be downloaded to the board.)
- 2011-05-09 21:09:07下载
- 积分：1
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exercise3
用verilog实现dsp与Fpga接口的同步设计，其功能包括读写操作及四个功能模块，采用两个fifo实现不同时钟域的地址与数据的转换，在quartus ii11.0环境下运行，运行此程序之前需运行将调用fifo。(Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modules, using two different clock domains to achieve fifo address and data conversion in quartus ii11.0 environment to run, run this program required before running calls fifo.)
- 2013-08-30 11:12:09下载
- 积分：1
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FDDDDRSDRAMP
一种基于FPGA 实现DDDR SDRAM的控制器
(DDDR SDRAM controller based on FPGA)
- 2012-08-29 23:52:53下载
- 积分：1
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用verilog写的很好的cpu core
用verilog写的很好的cpu core-using Verilog write a good cpu core
- 2023-06-03 16:40:03下载
- 积分：1
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FFT_VHDl
VHDL实现快速傅里叶变换，内附带资料以及源代码。(VHDL fast Fourier transform, within the supplied data and source code.)
- 2020-08-14 20:08:27下载
- 积分：1
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