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I do view on the VHDL design options for the CPLD or FPGA to achieve HDB3 code
我上期做的VHDL设计方案，用于在FPGA或CPLD中实现HDB3的编码-I do view on the VHDL design options for the CPLD or FPGA to achieve HDB3 code
- 2022-10-15 14:00:02下载
- 积分：1
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NIOS_i2sound_demo
在nios系统开发中的驱动i2c音频电路的代码,包括verilog代码,与相应的驱动代码(In the nios system development in the driver i2c code for the audio circuitry, including the verilog code, and the corresponding driver code)
- 2009-12-18 10:08:09下载
- 积分：1
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add16
designing of 16 bit adder using 4 bit adder using verilog code
- 2012-09-10 14:40:32下载
- 积分：1
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Synopsys使用基本步骤使用的集成工具，有用的好东西
使用synopsys的基本步骤，综合工具的使用说明，有用的好东西-Synopsys using the basic steps to use the integrated tools, useful good things
- 2022-04-06 15:39:11下载
- 积分：1
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bit
// Data port, granularity 8
// -*- Mode: Verilog -*-
// Filename : wb_master.v
// Description : Wishbone Master Behavorial
// Author : Winefred Washington
// Created On : 2002 12 24
// Last Modified By: .
// Last Modified On: .
// Update Count : 0
// Status : Unknown, Use with caution!
// Description Specification
// General Description: 8, 16, 32-bit WISHBONE Master
// Supported cycles: MASTER, READ/WRITE
// MASTER, BLOCK READ/WRITE
// MASTER, RMW
// Data port, size: 8, 16, 32-bit
// Data port, granularity 8-bit
// Data port, Max. operand size 32-bit
// Data transfer ordering: little endian
// Data transfer sequencing: undefined-//-*- Mode: Verilog-*-
// Filename : wb_master.v
// Description : Wishbone Master Behavorial
// Author : Winefred Washington
// Created On : 2002 12 24
// Last Modified By: .
// Last Modified On: .
// Update Count : 0
// Status : Unknown, Use with caution!
// Description Specification
// General Description: 8, 16, 32-bit WISH
- 2023-03-16 01:05:04下载
- 积分：1
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verilog_ad0809 cpld control
verilog_ad0809 cpld control
- 2022-03-17 13:00:05下载
- 积分：1
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11880608svpwm
正弦波电流驱动的无刷直流电机性能分析，通过分析方波电流驱动与正弦波电流比较，得出正弦波电流驱动电机性能较好(Sine wave current drive brushless DC motor performance analysis, by analyzing the square-wave current drive with sine wave current comparison, the sine-wave current drive motor performance is better)
- 2013-06-17 11:16:46下载
- 积分：1
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简单的键盘接口模块程序
一个简单的键盘接口模块程序，对键盘输入的数据和时钟信号进行过滤。过滤后的数据信号PS2Df将被送入两个11位移位寄存器中(A simple keyboard interface module program filters keyboard input data and clock signals. The filtered data signal PS2Df will be fed into two 11-bit displacement registers.)
- 2020-06-24 02:00:02下载
- 积分：1
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srio
fpga平台实现srio通信，以及srio端口寄存器设计。(FPGA platform to achieve sRIO communication, as well as sRIO port register design.)
- 2017-07-09 16:52:45下载
- 积分：1
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report
report for a report for a class
- 2019-04-17 21:19:15下载
- 积分：1
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