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JIAOTONGDENG
用VERILOG实现 交通灯控制，且运行正确，希望有帮助(Use VERILOG implementation traffic light control, and operation right, hope to have help)
- 2014-01-05 20:38:03下载
- 积分：1
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CME3000FPGADevelopment-
针对京微雅阁的CME300 FPGA教程，里面有几个例程，并附有源代码，初学者可尽快入门。(For Beijing micro Accord CME300 FPGA tutorial, there are a few routines, with source code, beginners can start as soon as possible.)
- 2013-08-19 18:01:21下载
- 积分：1
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bt656_decode
将嵌入式BT656格式数据解码出带行场同步信号的YCbCr422格式数据(Decoding Embedded BT656 Format Data to YCbCr422 Format Data with Field Synchronization Signa)
- 2021-01-28 10:38:35下载
- 积分：1
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本项目是基于SR和D触发器的使用vhdl.this是100正确的内容。
this project is based on sr and d flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering.
Here dataflow techniques and behavioural
-this project is based on sr and d flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering.
Here dataflow techniques and behavioural
- 2022-06-27 01:31:46下载
- 积分：1
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fpq
介绍了基于VHDL的可编程分频器在波形发生器中的应用的方法，利用这一方法，
可使波形频率在大范围内变化。()
- 2007-07-24 15:46:43下载
- 积分：1
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ag-overview
说明： agilex fpga description
- 2019-05-13 18:21:04下载
- 积分：1
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16 point radix 2
使用 c languageit 的 16 点基 2 fft 代码将 16 点时间域序列转换为频率域
- 2022-10-05 23:25:03下载
- 积分：1
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emif_tt
实现dsp与fpga的emif的verilog异步实现，可实现异步读写以及相应功能模块控制，文件中包含仿真后的波形图形以及仿真测试程序，运行环境quartus ii11.0，仿真环境mmodelsim se 6.5d(Achieve dsp and fpga verilog asynchronous implementation of the emif, enabling asynchronous reading and writing as well as the corresponding function module control, the document contains graphics, and after the simulation waveform simulation testing procedures, operating environment quartus ii11.0, simulation environment mmodelsim se 6.5d)
- 2020-12-04 15:59:23下载
- 积分：1
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一篇用VHDL实现快速傅立叶变换的论文
一篇用VHDL实现快速傅立叶变换的论文，包括原理分析和代码实现，印度圣雄甘地大学M.A.学院提供(VHDL with a Fast Fourier Transform papers, including the principle of analysis and implementation of the code, the Mahatma Gandhi Institute of the University of Marat)
- 2004-10-05 11:06:01下载
- 积分：1
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16-bit-CPU
单周期16位CPU的设计,我们的计算机组成原理课设，可以实现R型、I型和J型指令，内有报告和指导书(Single-cycle 16-bit CPU design, our Principles of Computer Organization class set, you can achieve R-type, type I, and J-type instructions, reports and instructions)
- 2020-08-02 10:28:35下载
- 积分：1
