-
qpsk
说明： 载波同步是QPSK信号相干解调的一项关键技术。(Carrier synchronization signal coherent QPSK demodulation is a key technology.)
- 2008-10-07 10:12:23下载
- 积分：1
-
7SegmenAngka
说明： asssembly ccode to turn on 7 segmen
- 2019-12-17 09:53:09下载
- 积分：1
-
PCI_arbi
PCI arbi verilog source code
- 2009-03-29 18:04:41下载
- 积分：1
-
DLX-pipeline-in-verilog
verilog实现DLX指令集5段流水线(5 stage DLX pipeline implemented in verilog)
- 2013-08-24 22:59:48下载
- 积分：1
-
In terms of hardware decimal to binary will be no need to use adder computing th...
在硬件方面十进制到二进制将不需要采用加法器计算的方式，大大减少了计算时间。
- 2022-07-24 14:57:38下载
- 积分：1
-
8位十六进制频率计设计 根据频率的定义和频率测量的基本原理，测定信号的频率必须有一个脉宽为1s的输入信号脉冲计数允许信号；1s计数结束后，计数值被锁入锁存器，计...
8位十六进制频率计设计 根据频率的定义和频率测量的基本原理，测定信号的频率必须有一个脉宽为1s的输入信号脉冲计数允许信号；1s计数结束后，计数值被锁入锁存器，计数器清零，为下一测频计数周期做好准备。测频控制信号可由一个独立的发生器（FTCTRL）来产生。-8-bit hexadecimal Cymometer designed in accordance with the definition of frequency and frequency of the basic principles of measurement to determine the frequency of the signal must have a pulse width of the input signal for 1s permit pulse counting signal 1s counting after the total value was locked into the lock depositors, counters cleared for the next count cycle frequency measurement ready. Frequency control signal generator may be an independent (FTCTRL) to generate.
- 2022-06-19 17:20:21下载
- 积分：1
-
top
脉冲多普勒雷达回波信号相干积累的VHDL源程序(pulse Doppler radar echo signal coherent accumulation of VHDL source)
- 2021-04-22 20:28:48下载
- 积分：1
-
code
其中两个项目自己做的：一个是雷达模拟跟踪，基于FPGA/CPLD的，里面包含了PCB和VHDL码，还有一个是SDIO的驱动程序（包括PCB原理图，SDIO协议方面的资料还有就是源码，这项目可用），还有一些嵌入式方面的资料，如TCP/IP协议栈的实现，FPGA的一些仿真实例(Two of the projects themselves to do: a tracking radar simulator is based on FPGA/CPLD)
- 2007-10-17 16:54:10下载
- 积分：1
-
all passed, I was carefully designed, fully meet the requirements of beginners....
全部通过，是我的精心设计，完全满足初学者的要求。0-99自动记数-all passed, I was carefully designed, fully meet the requirements of beginners. 0-99 automatic counting
- 2022-05-05 06:11:20下载
- 积分：1
-
mac
基于网口的收发数据及解析数据内容的verilog代码实现(Based on the Internet port to send and receive data and parse the contents of the data verilog code)
- 2017-04-24 10:13:55下载
- 积分：1
