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用vhdl实现脉冲宽度可控的一简单程序 仿真环境MAXPLUS
用vhdl实现脉冲宽度可控的一简单程序 仿真环境MAXPLUS--use VHDL to achieve controllable pulse width of a simple process simulation environment Segments-
- 2022-07-22 06:50:26下载
- 积分：1
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HART-HT2015
HART 官方资料-HART协议采用基于Bell202标准的FSK频移键控信号，在低频的4-20mA模拟信号上叠加幅度为0.5mA的音频数字信号进行双向数字通讯，数据传输率为1.2kbps。(Official information-HART HART protocol based Bell202 standard frequency shift keying FSK signal at low frequencies 4-20mA analog signal amplitude is 0.5mA superimposed on the two-way audio digital signal digital communication, data transfer rate of 1.2kbps.)
- 2013-07-16 17:23:16下载
- 积分：1
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FSK
2FSK的matlab仿真，叠加了高斯白噪声(2FSK matlab simulation, superimposed on a Gaussian white noise)
- 2021-04-13 02:58:56下载
- 积分：1
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VHDL_PS2
Spartan3e keyboard ps2
- 2010-01-28 18:38:40下载
- 积分：1
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展位乘数 VHDL 源代码
8位有符号编码的整数基改性
- 2022-06-14 01:22:33下载
- 积分：1
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E5_1_AskMod
matlab仿真2ask和4ask.可观察信号的时域波形和频谱图。(Matlab simulation 2ask and 4ask. Can observe the signal time domain waveform and spectrum.)
- 2021-03-08 17:29:28下载
- 积分：1
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Rs232_Trans
controller for sending serial data at different speeds
- 2009-04-28 02:41:14下载
- 积分：1
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Xilinx_FPGA_FFT_Application_Note
Xilinx FPGA中FFT IP核的使用笔记，内部有FFT硬核的端口说明和具体设置以及源代码，对于数字信号处理研究人员，能图像处理、雷达成像、实时通信开发人员较多的开发时间！(Xilinx FPGA in the FFT IP core using a laptop internal hard core of the FFT port description and specific settings as well as the source code for digital signal processing, image processing, radar imaging, real-time communications developers more development time!)
- 2013-04-23 09:34:31下载
- 积分：1
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18_vga_test
说明： 基于Xilinx Spartan6系列的fpga的VGA实现(Based on Xilinx Spartan6 series fpga VGA implementation)
- 2019-04-01 13:47:46下载
- 积分：1
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SPI serial bus interface Verilog realization elaborate on the realization of the...
SPI串行总线接口的Verilog实现，详细讲解实现过程。-SPI serial bus interface Verilog realization elaborate on the realization of the process.
- 2022-11-13 03:50:04下载
- 积分：1
