一个嵌入式RISC CPU 的Verilog 设计源码,可综合。内含详细的设计文挡。-an embedded RISC CPU design Verilog source code can be integrated. Detailed design containing the text block.
本程序利用MULTI-ICE通过JTAG口下编译的可执行程序*.bin文件在线烧写flash-the procedures used MULTI- JTAG ICE through the mouth under compiler executable file-*. bin burning flash