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基于VHDL+FPGA的DDS信号发生设计，已经通过调式
基于VHDL+FPGA的DDS信号发生设计，已经通过调式-Based on VHDL+ FPGA design of the DDS signal has been through mode
- 2022-06-28 11:38:23下载
- 积分：1
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AD_FIFO
简单的Verilog程序，针对音频实验板的AD到DA调通试验，下载执行前请按照自己试验环境更改设置(Simple Verilog program for test the AD to DA loop of universal audio test platform.
Please configure it according to the test environment before download and implement the program to FPGA)
- 2013-01-26 00:47:37下载
- 积分：1
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DE2_115_Synthesizer
FPGA implementation of simple Multi-tone Electronic Keyboard using DE2-115 board with a PS/2 keyboard and speaker
- 2013-08-20 19:48:32下载
- 积分：1
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FPGA设计的I2C总线控制器的MASTER端的程序
FPGA设计的I2C总线控制器的MASTER端的程序-FPGA Design of I2C Bus Controller MASTER-side procedures
- 2022-03-14 08:16:35下载
- 积分：1
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xilinx-FPGA
xilinx FPGA技术详解,从设计流程到设计注意点(xilinx FPGA technology Detailed Design points, from the design process to)
- 2012-08-10 13:07:41下载
- 积分：1
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fftshixian
基于FPGA编写的verilog代码，在xilinx上仿真实现FFT变换(FPGA-based verilog code written in xilinx FFT transform Simulation)
- 2015-04-05 11:42:08下载
- 积分：1
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20190717
说明： uart documentation, july 17, 2019. the document describes the basics of verilog programming and how to implement them on an fpga device
- 2020-06-21 21:40:01下载
- 积分：1
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JPEG标准下图象压缩的vhdl实现工程，文件包括一个图像。
JPEG标准下图象压缩的vhdl实现工程，文件包括一个图像。-JPEG image compression standard works of VHDL realize that the document includes an image.
- 2022-02-24 18:44:31下载
- 积分：1
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brazorobotico
Brazo robotico proyecto para laboratorio
- 2015-02-21 05:57:29下载
- 积分：1
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一款240＊128的LCD模块在ALTERA FPGA NIOS中的应用，自己写的AVALON总线IP，包括所有源码，可轻松用于NIOS中，供大家参考...
一款240＊128的LCD模块在ALTERA FPGA NIOS中的应用，自己写的AVALON总线IP，包括所有源码，可轻松用于NIOS中，供大家参考-A 240* 128 LCD module in the ALTERA FPGA NIOS application, write your own AVALON Bus IP, including all source code can be easily used in NIOS for reference
- 2022-07-03 08:05:54下载
- 积分：1
