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verilog HDL语言编写的键盘扫描程序，考虑以确定关键的博…
Verilog HDL编写的键盘扫描程序，考虑了判断按键弹起的问题。程序按一定的频率用低电平循环扫描行线，同时检测列线的状态，一旦判断有一列为低则表示有键被按下，停止扫描并保持当前行线的状态，再读取列线的状态从而得到当前按键的键码；等待按键弹起：检测到各列线都变成高点平后，重新开始扫描过程，等待下一次按键。-Written in Verilog HDL keyboard scanner, taking into account to determine key bounce problem. Program according to a certain frequency of scan lines with low-level circulation lines, while testing out the state line, once the judge has said there is a classified as low-key is pressed, stop the scan and to maintain the current line-line state, and then read out line state to get the current keys key codes to wait for key pop-up: To detect the lines at all out into a high level after the re-start the scanning process, waiting for the next key.
- 2022-05-07 15:33:47下载
- 积分：1
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由VHDL 语言实现的数控分频
利用的是QUARTUES环境已经得到验证...
由VHDL 语言实现的数控分频
利用的是QUARTUES环境已经得到验证-By the NC VHDL language is the use of sub-frequency QUARTUES environment has been tested
- 2023-01-20 00:20:04下载
- 积分：1
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LMP
利用LMP的20bit counter,比自带的cout进位要快的多。已经同错综合和时序仿真。-LMP
- 2022-01-25 18:35:46下载
- 积分：1
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izhihuangenzongPWMnb
三相电流滞环跟踪PWM逆变器。逆变电路负载电流与指令电流比较产生PWM波形。经验证可很好实现功能。(The three-phase hysteresis current tracking PWM inverter. Load current command current of the inverter circuit generating a PWM waveform. Proven functions well.)
- 2012-11-26 11:56:56下载
- 积分：1
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led
基于fpga的led点阵控制系统软件程序设计(Led dot matrix control system based on fpga software program design)
- 2013-01-14 11:50:35下载
- 积分：1
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uart16550 ip core UART VHDL source code
uart16550 ip core 通用异步收发器vhdl源代码-uart16550 ip core UART VHDL source code
- 2022-07-11 01:23:07下载
- 积分：1
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qiangdaqi
本程序为四路抢答器verlog HDL语言工程实例。(This program is four Responder verlog HDL language engineering examples.)
- 2013-10-30 14:48:21下载
- 积分：1
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FPGA realization of DDS with the schematic diagram, structural clarity, the use...
用FPGA实现DDS的原理图，结构清晰，采用总线方式与外部单片机通信-FPGA realization of DDS with the schematic diagram, structural clarity, the use of bus-way communication with the outside Singlechip
- 2022-04-16 10:26:17下载
- 积分：1
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vhdl testbench的编写，textio的编写是一个难点，也是一个重点，而这是本人搜集的多篇关于textio的文章，同时附有简单注释!...
vhdl testbench的编写，textio的编写是一个难点，也是一个重点，而这是本人搜集的多篇关于textio的文章，同时附有简单注释!-vhdl testbench preparation, textio the preparation is a difficult, but also a focus, and this is my collection of articles on textio the article, at the same time with a simple note!
- 2022-10-01 22:10:03下载
- 积分：1
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subway-ticket-vending-system
本设计是基于FPGA设计一个地铁自动售票系统。 本设计采用自顶向下的模块化设计方法，基于FPGA使用VHDL语言设计制作一个地铁自动售票控制系统，该系统能出售2条线路3种不同价位的票，完成售票、找零、显示等功能。(The design is based FPGA design of a subway ticket vending system. This design uses a top-down, modular design method, a subway ticket vending control system based on FPGA using VHDL language design, the system can sell two lines of different priced tickets, complete the ticket, give change, display and other functions .)
- 2013-02-27 12:59:49下载
- 积分：1
