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vhdl code for decoder and detemines the basic mechanism of gates of decoder
vhdl code for decoder and detemines the basic mechanism of gates of decoder
- 2022-01-25 15:11:52下载
- 积分:1
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dds(1)
基于DDS的信号发生器设计。DDS,FPGA,Verilog。(Design of signal generator based on DDS.DDS,FPGA,Verilog.)
- 2017-07-11 16:36:38下载
- 积分:1
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Verilog语言编写的电话计费系统,这只是源代码,需要在quartusII等软件下运用...
Verilog语言编写的电话计费系统,这只是源代码,需要在quartusII等软件下运用-Verilog language telephone billing system, this is only the source code, the need to use software such as quartusII
- 2023-01-23 23:25:03下载
- 积分:1
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updown
VHDL Programmes -2 for dumping on FPGA
- 2014-02-12 00:22:46下载
- 积分:1
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lcd_176
说明: VHDL code for LCD for use with AGM FPGA
- 2020-01-19 17:04:44下载
- 积分:1
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它的译码器的VHDL程序
it s vhdl program for decoder
- 2022-11-23 15:15:04下载
- 积分:1
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胡尚存 iuh h,ggygy dddtr 化为 ytf
hbhj bhj 南非 hj jh jh kj kje fkjdh kjh kjhfuhfhuu så s jekak o hfufuu ann anfuuan sjfk f4 77 57874 98 erj ierh ehlf hfjshf sieh fjsaæ kh fkjeh fæah fæakjfhhbhj bhj 南非 hj jh jh kj kje fkjdh kjh kjhfuhfhuu så s jekak o hfufuu ann anfuuan sjfk f4 77 57874 98 erj ierh ehlf hfjshf sieh fjsaæ kh fkjeh fæah fæakjfhhbhj bhj 南非 hj jh jh kj kje fkjdh kjh kjhfuhfhuu sås jekak o hfufuu ann anfuuan sjfk f4 77 57874 98 erj ierh ehlf hfjshf sieh fjsaæ kh fkjeh fæah fæakjfhhbhj bhj 南非 hj jh jh kj kje fkjdh kjh kjhfuhfhuu så s jekak o hfufuu ann anfuuan sjfk f4 77 57874 98 erj ierh ehlf hfjshf sieh fjsaæ kh fkjeh fæah fæakjfhhbhj bhj 南非 hj jh jh kj kje fkjdh kjh kjhfuhfhuu så s jekak o hfufuu ann anfuuan sjfk f4 77 57874 98erj ierh ehlf hfjshf sieh fjsaæ kh fkjeh fæah fæakjfhhbhj bhj 南非 hj jh jh kj kje
- 2023-02-27 19:30:03下载
- 积分:1
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WA
说明: QUARTUS2 16.9 VHDL FPGA ENDAT2.2
- 2020-11-24 17:50:21下载
- 积分:1
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RISC
说明: URISC的RTL级设计,Verilog代码(Design: URISC RTL Verilog)
- 2019-06-16 23:07:39下载
- 积分:1
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100_Power_Tips_for_FPGA_Designersi
fpga高手设计实战真经100则,最新的FPGA英文书籍,值得参考学习(100 Power Tips for FPGA Designers,The new FPGA English books, worth learning)
- 2013-12-06 19:40:43下载
- 积分:1