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基于nios ii 控制altera de1 开发板上iic总线实现与at24c02通信
基于nios ii 控制altera de1 开发板上iic总线实现与at24c02通信-Based on nios ii controlled altera de1 Development Board iic bus for communication with the at24c02
- 2022-03-16 00:16:13下载
- 积分：1
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NIOS_TIMER
很不错的资源哦，这是我在实验室当年总结的关于nios timer的程序段(nios timer)
- 2014-06-18 09:13:42下载
- 积分：1
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datamux
dataflow muliplexer in FPGA
- 2010-01-12 21:59:04下载
- 积分：1
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Viterbi译码器的编解码器的设计
用Verilog实现
Viterbi译码器的编解码器的设计
用Verilog实现-Viterbi decoder。Verilog
- 2022-09-18 21:30:03下载
- 积分：1
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SPI_tx_ATtiny2313
ya 3an zok omkom 9a7ba
- 2014-08-12 02:41:54下载
- 积分：1
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my_digital_clock
数字钟，数字电子技术课程设计常用内容，基于basys3平台(Digital clock, digital electronic technology curriculum design commonly used, based on the basys3 platform)
- 2015-06-25 19:59:57下载
- 积分：1
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verilogsram
FPGA Verilog HDL 读写SRAM(SRAM FPGA Verilog HDL to read and write)
- 2012-11-11 11:41:04下载
- 积分：1
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SD_rtl
用verilog实现sd卡读写，亲测可用(Implementation of SD card read and write with Verilog)
- 2020-12-27 21:49:02下载
- 积分：1
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verilog program for iic bus design. the pakege includes iic protocl master progr...
Verilog数字系统设计教程【夏宇闻】原书第十章：IIC总线接口模块设计代码包-verilog program for iic bus design. the pakege includes iic protocl master program and behavel slavle program, even includes testbench and data bat files.
- 2022-01-31 13:13:45下载
- 积分：1
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baseband_verilog
verilog实现的基带信号编码，整个系统分为六个模块，分别为：时钟模块,待发射模块,卷积模块,扩频模块,极性变换和内插模块,成型滤波器(verilog implementation baseband signal coding, the entire system is divided into six modules, namely: the clock module, to be launched modules, convolution module, spread spectrum modules, polarity transform and interpolation modules, forming filter)
- 2009-10-08 10:19:34下载
- 积分：1
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