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这是FPGA的Spartan 3E基础工程文件。该项目是基于VGA游戏…
this fpga spartan 3e based project file .the project is the game based on vga.
this file contains 2,20,25,400Hz clock generating file as per required for the project.-this is fpga spartan 3e based project file .the project is the game based on vga.
this file contains 2,20,25,400Hz clock generating file as per required for the project.
- 2023-02-25 10:20:03下载
- 积分：1
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E5_1_AskMod
matlab仿真2ask和4ask.可观察信号的时域波形和频谱图。(Matlab simulation 2ask and 4ask. Can observe the signal time domain waveform and spectrum.)
- 2021-03-08 17:29:28下载
- 积分：1
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usbhostslave
说明： USB主机和设备的verilog代码，实现了USB1.1协议规范的要求(USB host and equipment Verilog code to achieve the USB 1.1 protocol specification requirements)
- 2005-09-13 11:34:09下载
- 积分：1
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vhdl
code for fft non synthesisable in xilinx ise
- 2013-09-30 13:16:13下载
- 积分：1
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murata ads 2011 model
ADS是安捷伦科技公司的EDA软件这个库的等效电路数据使用ADS2011，后来只。（请参阅ADS2009U1有关图书馆的信息和更早版本）
- 2023-09-10 01:30:04下载
- 积分：1
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用vhdl做的计算机组成原理课程设计的资料，实现加法运算，进行求和，仿真实例等资料！...
用vhdl做的计算机组成原理课程设计的资料，实现加法运算，进行求和，仿真实例等资料！-Vhdl to do with the computer information on the composition of curriculum design principles to achieve the addition operation, a sum, simulation examples, etc.!
- 2022-03-18 00:56:15下载
- 积分：1
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VHDL电子抢答器的实现。有多个文件，主控件是用图行实现。其余各功能模块用VHDL实现...
VHDL电子抢答器的实现。有多个文件，主控件是用图行实现。其余各功能模块用VHDL实现-VHDL electronic Responder realized. A number of documents, the main controls are using maps the bank. The remaining modules using VHDL
- 2022-03-14 00:36:42下载
- 积分：1
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signaltap_user_guide
signaltap 中文说明，内容详细。
ALTERA signaltap USER GUIDE IN CHINESE(ALTERA signaltap USER GUIDE IN CHINESE)
- 2011-12-03 23:50:21下载
- 积分：1
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1. For the key input, please join the voice output circuit, representing the key...
1对于按键输入，请加入语音输出电路，代表按键sw1反馈的音频信息。每次按下sw1按钮时，它们都会发出0.1秒1KHz的声音。
- 2022-03-02 14:32:00下载
- 积分：1
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Verilog ADPLL文件和testbench。V
verilog ADPLL file with testbench.v
- 2022-02-25 04:56:13下载
- 积分：1
