-
CPU-
五级流水线CPU实现（带Hazard），还没来得及实现Cache求高人指教(pipeline CPU with Hazard)
- 2020-12-03 12:59:24下载
- 积分：1
-
verilog user guide
verilog语法说明，包含verilog golden reference guide，verilog 2001语法(verilog golden reference guide)
- 2018-05-08 22:50:16下载
- 积分：1
-
math_real
in this code very useful for designing real number concept
- 2013-11-19 19:54:40下载
- 积分：1
-
led
控制8个发光二极管中的一个发光二极管发光，其它7个发光二极管都出于截止状态，发光二极管的导通顺序按照向左或向右两个方向移动，并且通过按键控制发光二极管循环发光移动的方向。(Control of a light-emitting diode light-emitting eight light-emitting diodes, the other seven light-emitting diodes for the cut-off state, light-emitting diode conduction order in accordance with the left or right move in both directions, and light-emitting diode cycle luminous button control mobile direction.)
- 2012-11-09 12:33:57下载
- 积分：1
-
123
说明： 系统介绍了数字开发系统平台FPGA设计中的部分技巧 对于FPGA开发研究人员具有一定的指导和帮助意义(Systematic introduction of digital development platform FPGA design techniques for FPGA development of some of the researchers have some sense of guidance and help)
- 2011-03-24 10:34:07下载
- 积分：1
-
步进电机
此代码是用于旋转一个步进电机所需的方向。
- 2022-10-22 10:05:04下载
- 积分：1
-
MX25L6445E--Verilog--v1.18
MX25L6445E开发时间，Verilog语言(MX25L6445E development time, Verilog language)
- 2011-07-20 15:11:31下载
- 积分：1
-
fpga_dsp_simple
dsp和fpag通信的测试程序，包含整个工程和signaltap测试信号。(the the dsp and fpag communications test procedures, including the entire the engineering and signaltap test signal.)
- 2013-04-14 15:17:20下载
- 积分：1
-
Using VHDL realize the divider, so very, simulation adopted
用VHDL实现的除法器,非常好使,仿真通过了-Using VHDL realize the divider, so very, simulation adopted
- 2023-06-11 22:15:03下载
- 积分：1
-
VHDL language design stopwatch, timer function of the realization, the realizati...
VHDL语言设计的秒表，实现计时功能，实现报时功能，并且通过硬件实验。-VHDL language design stopwatch, timer function of the realization, the realization of time functions, and through hardware experiments.
- 2022-09-16 02:55:02下载
- 积分：1
