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                        PID controller verilog源代码
                        
                          The PID controller IP core performs digital proportional–integral–derivative controller (PID controller) algorithm. The algorithm first calculates the error between a measured value (PV) and its ideal value (SP), then use the error as an argument to calculate the manipulate value(MV). The MV will adjust the process to minimize the error. It can be used to calculate duty cycle for PWM (Pulse Width Modulation).                         
                            - 2022-09-23 12:05:03下载
- 积分:1
 
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                        (7,4)汉明码
                        
                          汉明码学习,以(7,4)为例,仿真正常。(Hamming code learning, taking (7, 4) as an example, the simulation is normal.)                         
                            - 2021-03-29 17:19:10下载
- 积分:1
 
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                        zybo1_FPGA_Design_Flow_using_Vivado
                        
                          zybo1_FPGA_Design_Flow_using_Vivado,基于zybo实现加法器功能,zybo简单例程。                         
                            - 2022-07-07 21:26:49下载
- 积分:1
 
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                        rs_204_188----v1.0
                        
                          RS 编码和解码Verilog Code, 实现了RS(204,188)的编码和译码;(RS Coding and Decoding Verilog code, implement  RS(204,188)  )                         
                            - 2021-03-25 20:29:14下载
- 积分:1
 
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                        基于FPGA的深度学习加速器设计与实现
                        
                          基于FPGA的深度学习加速器设计与实现,帮助你增加对深度学习的理解,而且作为中文,很适合国内学者。(Design and implementation of deep learning accelerator based on FPGA)                         
                            - 2017-10-16 16:54:19下载
- 积分:1
 
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                        7-segment
                        
                          VHDL Design of BCD to 7-segment decoder 
using PROM                         
                            - 2009-05-04 02:44:02下载
- 积分:1
 
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                        交通灯 通过测试 有测试文件
                        
                          交通灯 通过测试 有测试文件,其中timer_test.v为测试文件,可用于modelsim仿真测试用,timer.v为分频模块,可调节分频常数以适应不同的时钟频率,使输出时钟频率达到1Hz。light.v为交通灯控制灯的亮灭信号,digitron.v为交通灯数码管控制倒计时模块。整个交通灯为四相模式,有左转,倒计时为四个路口的。希望对共同学习verilog的同学有帮助!                         
                            - 2022-06-01 13:18:39下载
- 积分:1
 
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                        Divider-vhdl
                        
                          This is a divider, which is depicted as well.
It is a programming language Vhdl.                         
                            - 2013-09-29 18:28:11下载
- 积分:1
 
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                        tb_modular
                        
                          说明:  Matlab to hdl code for Least_square testbench                         
                            - 2020-06-17 12:20:02下载
- 积分:1
 
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                        tsobbellh
                        
                          这是我本人自己开发的可用于256*256大小的图像进行sobel边缘检测的vhd文件,可在QuartusII或MaxplisII下综合与与仿真,并在FPGA上测试过。能进行修改支持其他大小图像的sobeel边缘检测,同时还能实现其它的图像模块化处理算法,例如高斯滤波,平滑等。
(This is my own development vhd file, can be used for 256* 256 size image sobel edge detection under QuartusII or MaxplisII synthesis and with simulation, and tested on FPGA. Can be modified to support other sobeel size image edge detection, while still achieving other image the modular processing algorithms, such as Gaussian filtering and smoothing.)                         
                            - 2012-08-23 22:17:19下载
- 积分:1