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zong
说明: quartusII 9.1,位同步提取电路,可以实现位同步时钟提取,其中包括分频器,和由D触发器以及与门组成的鉴相器模块。(Quartus II 9.1, bit synchronous extraction circuit, can realize bit synchronous clock extraction, including frequency divider, phase discriminator module composed of D trigger and and gate.)
- 2020-01-11 13:40:31下载
- 积分:1
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BISS-B---Stimulate_OK
BISS-B 源代码。包含传感器模式和寄存器模式(BISS-B source code. Includes sensor mode and register mode)
- 2021-03-15 19:29:22下载
- 积分:1
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aulap3_IsadoraStangarlin
Code developed in classroom
- 2017-09-28 00:51:06下载
- 积分:1
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ANALYSIS-OF-ALL-GATES
ANALYSIS OF ALL GATESS
- 2013-11-12 13:33:55下载
- 积分:1
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CJ2
关键词:清华大学计算机系 计算机组成原理大实验 多周期cpu工程源码,内含中断,串口,以及31个指令的实现,读写内存,控制器,ALU,寄存器,分频等模块,小作业什么的可以直接从里面摘抄,为学弟学妹造福(Keywords: Department of Computer Science Computer Composition Principle experimental multi-cycle the cpu Engineering source for the benefit of mentees)
- 2020-12-29 10:09:01下载
- 积分:1
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FIR filter basic verilog code for implementation
FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
- 2022-07-11 03:20:47下载
- 积分:1
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FPGA_5
无SDRAM的PCI采集,给出PCI采集的FPGA程序,桥芯片也为PLX9054,已验证通过(No SDRAM, PCI capture, given FPGA PCI acquisition program, bridge chips for PLX9054, has been verified by)
- 2015-01-07 22:57:46下载
- 积分:1
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riscmcu VHDL,包含仿真平台和文档进行显示
riscMCU的VHDL实现,内附有modelsim仿真testbench和文档说明-riscMCU VHDL, modelsim containing a simulation testbench and documentation shows
- 2022-05-29 16:45:22下载
- 积分:1
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这是兼容的CPU 8051 VHDL语言,它不是一个侵权。上帝保佑!
这是兼容的8051 VHDL CPU实现,应该不算侵权吧。 上帝保佑!-This is compatible CPU 8051 VHDL, it is not a tort. God bless!
- 2022-10-01 01:00:03下载
- 积分:1
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应用VHDL语言将高稳晶振分频得到1pps,使用GPS的1pps信号作为触发...
应用VHDL语言将高稳晶振分频得到1pps,使用GPS的1pps信号作为触发-Application of VHDL language high stability crystal oscillator frequency to be 1pps, the use of GPS signals as a trigger of 1pps
- 2022-05-12 21:39:28下载
- 积分:1