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Verilog_135example
关于硬件描述语言Verilog的135个经典实例，从易到难，对Verilog的编程有很大的帮助。(About the Verilog hardware description language 135 classic example, from easy to difficult, for Verilog programming of great help.)
- 2013-06-17 10:29:43下载
- 积分：1
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一个可编程的间隔定时器的设计，8253要完成的功能，实…
设计一个可编程间隔定时器，完成8253的功能，实现以下几点要求：
1、 含有3个独立的16位计数器，能够进行3个16位的独立计数。
2、 每一种计数器具有六种工作模式。
3、 能进行二进制/十进制减法计数。
4、 可作定时器或计数器。
-The design of a programmable interval timer, 8253 to complete the function, realize the following requirements: 1, contains three independent 16-bit counter, capable of three independent 16-bit count. 2, each with six counter mode. 3, can be binary/decimal subtraction count. 4, can be used for the timer or counter.
- 2022-08-20 11:53:35下载
- 积分：1
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8_BUS
说明： BUS documentation and map reffereces
- 2020-06-25 19:40:02下载
- 积分：1
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shift_registers
Universal Shift Register
- 2009-06-12 17:29:13下载
- 积分：1
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SAR-ADC
Complete Successive approximation Analog to digital converter along with the source code
- 2013-04-21 23:42:03下载
- 积分：1
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I2C
关于I2C总线协议的verilog代码，里面包括了3个verilog代码(I2C bus protocol verilog code, which includes three verilog code)
- 2012-08-31 14:31:29下载
- 积分：1
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gps
基于fpga和dsp架构的gps接收机的设计和实现(Design and Implementation of gps Receiver Based on fpga)
- 2017-05-25 17:44:51下载
- 积分：1
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spi_hello
SPI接口测试程序，Xilinx参考设计，ML507硬件测试通过.(SPI interface test code，Xilinx reference design，tested on ML507 platform.)
- 2013-09-01 09:37:04下载
- 积分：1
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fffffff
如上图所示， Rst是低电平有效的系统复位信号，Clk是时钟信号。AB[5：0]是地址信号，DB[7：0]是数据信号，wr是低电平有效的写信号。start是启动信号。
模块中有一个64x8的双端口的存储器。系统复位结束后，可以通过AB、DB和wr信号向同步存储器写入数据。当写入64个数据后，给出一个Clk周期宽度的脉冲信号start，则系统从存储器0地址处开始读出数据，读出的8位数据从低位开始以3位为一组，每个时钟周期输出一组，即第一个时钟周期输出[2：0]位，第二个时钟周期输出[5：3]位，第三个周期输出1地址的[0]位和0地址的[7：6]位，直至将存储器中64x8数据全部输出。若最后一组不足三位，则高位补0。
(As shown above, Rst is an active-low system reset signal, Clk is a clock signal. AB [5: 0] is the address signal, DB [7: 0] is the data signal, wr write signal is active low. start is the start signal. Module in a dual port memory of 64x8. After the reset, you can write data to the synchronous memory by AB, DB and wr signals. When data is written to 64, given the width of a pulse signal Clk cycle start, the system begins to read the memory address 0, 8 data read out a low starting with three as a group, each clock outputs a set period, which is the first clock cycle of the output [2: 0] bits, the second clock cycle output [5: 3] position, the third cycle of the output of an address [0] and 0 address [7 : 6] bit, until all the data in memory 64x8 output. If the last group of less than three, the high 0s.)
- 2020-11-04 20:39:51下载
- 积分：1
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802-11-Frame_E_C
Frame Control field
Retry:
Set in case of retransmission frame
More fragments:
Set when frame is followed by other fragment
Power Management
bit set when station go Power Save mode (PS)
More Data:
When set means that AP have more buffered data for a
station in Power Save mode
- 2016-08-23 17:37:40下载
- 积分：1
