-
VHDLaVerilogcomplie(20151022105744)
一个关于VERILOG与VHDL混合编程,混合验证的资料(A hybrid programming on VERILOG and VHDL, mixed verification data)
- 2015-12-14 17:19:26下载
- 积分:1
-
AD_TLC549驱动程序
AD_TLC549驱动程序,Verilog开发,输出控制led点亮。
- 2023-07-21 05:35:03下载
- 积分:1
-
Synthesis_and_Fpga_Implementation_of_UAR
Synthesis and fpga implementation of UART
- 2018-12-03 14:06:02下载
- 积分:1
-
dds32_1
说明: 频率合成器实例模块设计。频率分辨率为32位DDS的VHDL程序(Frequency synthesizer module design example. 32-bit DDS frequency resolution of the VHDL program)
- 2011-04-14 13:45:22下载
- 积分:1
-
rs-codec(255-223)
这是rs(255,223)编码的verilog源程序。里面有:encode、decode、test-bench等文件。(This is rs (255,223) verilog source coding. Inside : encode, decode, test-bench and other documents.)
- 2021-05-13 00:30:02下载
- 积分:1
-
zhitouzi
原创。掷骰子游戏,VHDL,quartus,北京邮电大学数电实验,实现随机掷骰子游戏,在数码管显示点数,点阵显示输赢,有开机动画以及开机音乐,可实现多人游戏等(games, VHDL, quartus,experiments of BUPT, pure originality,random game, in the digital display dots, dot matrix display winning or losing, there are boot animation and boot music, multiplayer gaming can be achieved)
- 2020-12-24 20:49:04下载
- 积分:1
-
Verilog HDL 4bit_processor
RTL码由控制、alu、寄存器、keych模块等组成。。。
- 2023-04-12 17:35:03下载
- 积分:1
-
S03_基于ZYNQ的DMA与VDMA的应用开发
VIVADO dma以及vdma 使用文档 基于ZYNQ 7020(vivado DMA&VDMA example text of zynq)
- 2020-06-17 11:40:02下载
- 积分:1
-
Dice_game
VHDL Project for beginners. Electronic dice game. Perfect for Spartan devices.
- 2011-02-22 22:07:59下载
- 积分:1
-
myuart
使用verilog语言编写的异步串口模块,带有16级深的FIFO,它与DSP28335的SCI相似,可以帮助初学者更快地理解FPGA和DSP的硬件结构和编程思路(Use verilog language of asynchronous serial port module, FIFO with deep level 16, it was similar with DSP28335 SCI, can help beginners to understand faster the FPGA and DSP hardware structure and programming ideas)
- 2013-07-25 11:45:57下载
- 积分:1