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FIR
FIR滤波器的VHDL源代码及测试文件，已通过编译仿真，绝对正确。(FIR filter VHDL source code and test files, has passed the compiled simulation, absolutely correct.)
- 2021-04-15 11:08:54下载
- 积分：1
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sram_saa1117verilog
图像采集、存储控制verilog源代码，fpga控制SAA1117,采集数据存储到sram，仿真编译测试都能通过(Image acquisition, storage, control verilog source code, fpga control SAA1117, collecting data to sram, simulation tests can be compiled by)
- 2020-07-09 21:58:55下载
- 积分：1
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xapp1251
说明： 1. REVISION HISTORY
2. OVERVIEW
3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS
4. DESIGN FILE HIERARCHY
5. INSTALLATION AND OPERATING INSTRUCTIONS
6. SUPPORT
- 2020-11-07 09:49:49下载
- 积分：1
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codings
wavelet transform of a signal,it is important and useful code to trans form frequency to time domain
- 2013-11-10 15:10:32下载
- 积分：1
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percent
verilog编写的计算百分比模块(Verilog prepared by calculating the percentage module)
- 2005-03-08 21:33:38下载
- 积分：1
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- 2022-07-05 02:24:05下载
- 积分：1
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在nexys2数字cronometer
该项目是用VHDL编写的，并在Nexys2板套件的4个七段显示器中显示一个测微计的秒、分和小时。时间可以在开关0中停止，在按钮0中复位。显示方式与显示方式不同最小：分段到hr:min通过切换开关1
- 2022-11-12 07:55:03下载
- 积分：1
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JOP字节码获取的源码，很重要，具体FPGA中实现
JOP字节码获取的源码，很重要，具体FPGA中实现-JOP byte code access to the source code is important to achieve specific FPGA
- 2022-01-26 02:39:47下载
- 积分：1
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PC
说明： Verilog HDL语言编写的32位程序计数器（PC）完整工程及相应仿真，QuartusII7.2下编译通过可正常使用。(Complete engineering and simulation of Verilog HDL language of the 32-bit program counter (PC), QuartusII7.2 compiled through normal use.)
- 2012-09-06 09:07:47下载
- 积分：1
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vhdl设计事例,有助于FPGA初学着,High
vhdl设计事例,有助于FPGA初学着,High-Performance 1024-Point
Complex FFT-vhdl design examples, to help novice FPGA. High-Performance 1024-Point Complex FFT
- 2023-06-12 19:40:12下载
- 积分：1
