-
MP3-coder
In this design, it is assumed that a buffer sized as 1024x8 bits provides main data including scale factors and Huffman code bits to Huffman decoder.
Also, it is assumed that a memory with 1024x8 bits is ready for each component to write or read the output or input 576 frequency lines.(This folder contains three directories: Huffman, IMDCT and Filterbank, each of them
includes all the VHDL source codes of the component.)
- 2013-08-06 15:40:24下载
- 积分：1
-
virtex7_pcie_dma
FPGA开发PCIe的源码，采用VHDL语言，通过此源码，能更好的掌握PCIe总线，使开发者少走弯路，
- 2023-01-25 04:55:04下载
- 积分：1
-
DS28E01
用verilog语言实现加密芯片DS28E01的调用操作命令。(Using Verilog language to achieve the encryption chip DS28E01 call operation commands.)
- 2021-03-17 09:49:21下载
- 积分：1
-
IEEE Standard for Verilog 2005
IEEE Standard for Verilog 2005
- 2017-06-05 13:53:12下载
- 积分：1
-
VHDL.Programming
这是这本书的第四个版本，现在这个版本不仅提供了VHDL语言的覆盖面，但设计方法的信息，以及。此版本将指导读者通过创建一个VHDL设计的过程中，模拟设计，综合设计，放置和布线设计，使用的重要模拟验证的最终结果，新的技术，称为全速调试，提供了极其快速设计验证。在这个版本的设计，例如已被更新(This is the fourth version of the book and this version now not only provides VHDL language coverage but design methodology information as well. This version will guide the reader through the process of creating a VHDL design, simulating the design, synthesizing the design, placing and routing the design, using VITAL simulation to verify the final result, and a new technique called At-Speed debugging that provides extremely fast design verification. The design example in this version has been updated to reflect.)
- 2012-04-08 19:36:36下载
- 积分：1
-
Modelsim
不错的Quartus II 与modelsim结合仿真简介笔记，较为适合初学者，希望对大家有帮助！()
- 2008-06-06 18:16:53下载
- 积分：1
-
cpu-maxplus
MaxplusII编写的简易cpu，可实现简单加减法等操作(MaxplusII summary prepared by the cpu can realize simple addition and subtraction, etc)
- 2007-06-08 17:55:10下载
- 积分：1
-
Verilog module containing a synthesizable CRC function
//* polynomial: (0 1 8)...
Verilog module containing a synthesizable CRC function
// * polynomial: (0 1 8)
// * data width: 8-Verilog module containing a synthesizable CRC function
//* polynomial: (0 1 8)
//* data width: 8
- 2022-08-18 21:19:43下载
- 积分：1
-
add4bit
一位全加器的VHDL源码与TEST BENCH.XILINX下通过(A full adder and the VHDL source code through TEST BENCH.XILINX)
- 2009-07-20 08:18:37下载
- 积分：1
-
实现BCD码的加法，用VHDL实现，是书籍上配套的
实现BCD码的加法，用VHDL实现，是书籍上配套的-BCD ADDER，Using VHDL
- 2022-02-10 02:09:10下载
- 积分：1
