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vhdl的一个串行序列信号发生器的设计与实现
vhdl的一个串行序列信号发生器的设计与实现-vhdl sequence of a Serial Signal Generator Design and Implementation
- 2022-04-24 02:34:50下载
- 积分：1
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costas
载波同步，costas环，基于Verilog的载波同步环(Carrier synchronization, costas ring, based on Verilog carrier synchronization ring
)
- 2021-03-05 13:09:31下载
- 积分：1
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RS232
基于VHDL的RS232通讯程序,包含完整的源代码,锁脚文件以及下载文件,可直接下载使用(VHDL based on the RS232 communication procedures, including complete source code, locking pin, as well as download files documents can be directly downloaded using)
- 2008-07-27 13:19:28下载
- 积分：1
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xilinx平台DDR3设计教程之仿真篇_中文版教程
DRD3在Xlinix平台上的设计教程以及仿真(DRD3 design tutorial and Simulation on Xlinix platform)
- 2018-11-02 11:18:06下载
- 积分：1
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第七次课--视频图像DCT处理及水印嵌入
熟悉IIC协议总线协议，采用IIC总线对图像采集传感器寄存器进行配置，并转换为RGB565格式。
利用异步FIFO完成从摄像头输出端到SDRAM 和SDRAM 到VGA 接口各跨时钟域信号的传输和处理。
利用 SDRAM 接口模块的设计，实现了刷新、读写等操作；为提高SDRAM 的读写带宽，均采用突发连续读写数据方式；并采用乒乓操作实现 CMOS 摄像头与VGA的帧率匹配。
利用双线性插值方法实现对图像640×480到1024×768的放大操作。
完成VGA显示接口设计。(Familiar with IIC protocol bus protocol, IIC bus is used to configure the register of image acquisition sensor and convert it into RGB565 format.
Asynchronous FIFO is used to transmit and process signals across clock domain from camera output to SDRAM and SDRAM to VGA interface.
With the design of SDRAM interface module, refresh, read and write operations are realized. In order to improve the read and write bandwidth of SDRAM, burst continuous read and write data mode is adopted, and table tennis operation is used to achieve frame rate matching between CMOS camera and VGA.
The bilinear interpolation method is used to enlarge the image from 640*480 to 1024*768.
Complete the VGA display interface design.)
- 2020-06-25 04:00:02下载
- 积分：1
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MAX2 EPLD 的测试程序, VHDL语言编写.
MAX2 EPLD 的测试程序, VHDL语言编写.-MAX2 EPLD testing code, VHDL language.
- 2022-01-26 06:18:20下载
- 积分：1
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med_filter
基于图像处理的中值滤波VHDL源码,能够实现对图像的滤波(Based on the median filter VHDL source image processing, image filtering can be achieved)
- 2014-07-15 10:28:28下载
- 积分：1
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verilog hdl coding DDR sdram control for fpga
verilog hdl coding DDR sdram control for fpga -verilog hdl coding DDR sdram control for fpga
- 2022-03-23 21:20:26下载
- 积分：1
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反设计的VHDL例子，使用QuickLogic ECLIPS
VHDL examples for counter design, use QuickLogic eclips
- 2022-08-25 05:17:29下载
- 积分：1
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点阵汉字显示的VHDL原程序.综合实验课程的程序,完全可以用的 希望大家支持啊...
点阵汉字显示的VHDL原程序.综合实验课程的程序,完全可以用的 希望大家支持啊-Dot-matrix characters shown in the original VHDL program. Comprehensive experimental program procedures, can be used to hope you will support the ah
- 2022-03-25 16:49:49下载
- 积分：1
