-
Y312448.zip
基于VHDL的SDH专用芯片的TOP-DOWN设计，
内有全套源码以及图片，内容详尽，绝对真实可靠！(VHDL based on the SDH ASIC Design TOP-DOWN, which has a full set of source code, as well as pictures, and detailed, reliable and absolutely true!)
- 2008-05-12 19:21:03下载
- 积分：1
-
Some_classic_examples_of_VHDL_language_source_code
ＶＨＤＬ语言的一些经典实例源代码，包括状态机，时序电路，组合逻辑电路等(Some classic examples of VHDL language source code, including the state machine, sequential circuits, combinational logic circuits)
- 2010-07-11 12:50:06下载
- 积分：1
-
编码器信号转换程序
编码器信号的转换，用于控制打印机，UV平板打印机的喷头驱动输出信号，控制Y轴移动，需要将信号转换为运动控制器识别的信号才可以控制其运动。
- 2022-10-20 19:55:03下载
- 积分：1
-
mdio
用VIVADO软件编写的，实现以太网芯片88E1510中的mdio控制模块代码，并且含有VIO仿真文件(Written in VIVADO software, the realization of the Ethernet chip 88 e1510 mdio control module of code, and contains the VIO simulation file)
- 2020-09-16 14:37:55下载
- 积分：1
-
1
一个解决除法溢出的例子，可以学习到很多，注释很详细(A solution to the division overflow example, you can learn a lot, very detailed notes)
- 2013-12-24 09:19:13下载
- 积分：1
-
并行LMS均衡FPGA实现
实现FPGA的并行LMS均衡，主要是均衡计算权值系数的算法过程，verilog语言，模块的输入为输入的X信号，输出为权值系数W，以及最后的输出Y。实现了LMS 的并行均衡过程
- 2023-09-08 06:15:03下载
- 积分：1
-
PERI4-DM9000A
基于FPGA的DM9000A芯片的网络数据采集系统，基于NIOS架构，c语言编程，资料齐全，包含不止5个源程序，绝对受用！(FPGA-based the DM9000A chip network data acquisition system based on NIOS architecture, c programming language, the information is complete, contains more than 5 source code is absolutely good enough!)
- 2020-09-16 16:57:55下载
- 积分：1
-
codes
EKG SIGNAL PROCESSING THROUGH CORDIC
- 2013-09-29 01:46:17下载
- 积分：1
-
dr6—ise-F
用FPGA开发板的按键作为电子表的时间初值设置控制信号，数码管当前时间值输出。用按键选择分别输出：分、秒、1/10秒。(With FPGA development board button, as the time value of the electronic table, set the control signal, digital tube current time value output. Select output by buttons: minutes, seconds, and 1/10 seconds.)
- 2017-10-11 21:19:55下载
- 积分：1
-
capture-using-SCCB-and-FPGA
利用SCCB和FPGA实现视频采集的论文，对相关开发人员具有很强的参考价值！
(FPGA implementation using the SCCB and video collection of the papers, the relevant developer has a strong reference value !
)
- 2013-09-29 15:37:52下载
- 积分：1
