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1553B-BC-TEST
1553B总线BC端的编程例子,做通了对于一个RT的测试。对于其他的RT测试和程序的例子原理相同。(The BC end of the 1553B bus programming examples)
- 2020-12-06 21:29:21下载
- 积分:1
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DualPortRAM
此程序是Verilog HDL语言读写RAM的程序希望大家有用(This is Verilog HDL Promang)
- 2020-10-29 21:19:57下载
- 积分:1
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ahb_sramc
基于AHB总线的sram控制器,带有memory bist(SRAM controller based on AHB bus)
- 2018-05-19 20:47:28下载
- 积分:1
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viterbi
viterbi decode by verilog
- 2019-06-18 00:55:40下载
- 积分:1
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nerualnetwork
本文为通信专业硕士研究生的毕业论文。主要研究神经网络的FPGA实现及其在网络拥塞控制中的应用。
(In this paper, for the communications professional Master s thesis. Major study of the FPGA realization of neural networks and its application in network congestion control applications.)
- 2008-12-14 01:37:03下载
- 积分:1
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baugh wooley codes
这是用于阵列乘法器baugh wooley 。这是写Verilog代码。它表明8位阵列乘法。这是输入含有8,8每输出有15位
- 2023-06-03 10:00:03下载
- 积分:1
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AHB_to_Wishbone_Verilog
说明: 该源代码包是AHB总线到Wishbone总线的交接器,包括以下4个部分:RTL源代码,测试平台,软件测试程序,说明文档。(This source package is the AHB bus to Wishbone bus bridge(wrapper).It has the following 4 parts: RTL codes, testbench, software simulating files, help documents.)
- 2021-01-22 14:48:40下载
- 积分:1
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FPGA的I2S接收模块 audio_in_buff
说明: 用于FPGA的I2S接收模块,仅供学习和参考(audio-i2s receive.use fpga.)
- 2019-04-21 12:11:23下载
- 积分:1
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20181060261-李康_3
说明: 秒表的实现,有暂停清零功能,Quartus II(Stopwatch realization, has the pause clear function)
- 2020-12-26 15:56:03下载
- 积分:1
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UART module Verilog codes and guidance
Verilog codes of UART modules and guidances of UART
- 2022-05-19 07:09:53下载
- 积分:1