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multiplier_interface
verilog 写的工程,是个基于流水线的乘法器(verilog write the works, is based on a pipelined multiplier)
- 2012-09-21 10:04:54下载
- 积分:1
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Read_SPI_ADC
This VHDL code takes a clock, reset, Capture_EN and SPI data LT2315 ADC and generates SPI_CLK and SPI_nCS of it and reads 12-bit serial data ADC and returns 12-bit parallel data.
- 2015-10-13 14:43:13下载
- 积分:1
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青云开发的LCD模块LCM240128ZK3用于ALTERA的FPGA,自己写的AVALON总线IP核,供大家参考...
青云开发的LCD模块LCM240128ZK3用于ALTERA的FPGA,自己写的AVALON总线IP核,供大家参考-err
- 2022-04-07 09:35:28下载
- 积分:1
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OFDM_618
说明: 基于FPGA的OFDM同步,包含时钟模块、ROM读取模块、峰值检测模块、帧同步模块(OFDM synchronization based on FPGA includes clock module, Rom reading module, peak detection module and frame synchronization module)
- 2020-08-12 16:41:34下载
- 积分:1
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这是个vhdl编写的16bit的加减法器
这是个vhdl编写的16bit的加减法器-This is vhdl prepared by the modified instruments used in the 16bit
- 2022-02-15 07:17:54下载
- 积分:1
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Using FPGA realize DDS, can be frequency, amplitude from hardware to complete
用FPGA实现DDS,可变频,幅值由硬件完成-Using FPGA realize DDS, can be frequency, amplitude from hardware to complete
- 2022-04-02 05:52:39下载
- 积分:1
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基于NiosⅡ的2 de2_tvproject
本演示使用VGA输出和DVD播放器播放视频和音频输入
- 2022-01-26 03:44:01下载
- 积分:1
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HDB3-encoderauncoder
HDB3编码器与解码器,以及RTL图,使用Verilog HDL实现(HDB3 encoder and decoder, and RTL diagram, use Verilog HDL to implement)
- 2014-12-14 13:17:26下载
- 积分:1
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基于DE2-70开发板的VGA接口实现程序
基于DE2-70开发板的VGA接口实现程序,可在VGA屏幕上显示800*600分辨率的图像,刷新频率60Hz
- 2022-03-12 13:00:51下载
- 积分:1
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AlteraFPGA_CPLD
ALTERA FPGA CLPD
- 2010-04-11 14:52:36下载
- 积分:1