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ALTERA上DE2平台,利用内部50M Hz时钟,在数码管模拟显示时间(时分秒)。
ALTERA上DE2平台,利用内部50M Hz时钟,在数码管模拟显示时间(时分秒)。-ALTERA on DE2 platform, using internal 50M Hz clock, in the digital control simulation show time (hours minutes and seconds).
- 2022-04-17 01:14:39下载
- 积分:1
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HW2+李东方+2019211409
说明: 基于数据通路和控制器的高校简单PPM设计(PPM design based on datapath and controller)
- 2020-11-25 02:19:32下载
- 积分:1
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GAL16V8反汇编源程序JED2ABEL.C 把jec汇编成abel文件
GAL16V8反汇编源程序JED2ABEL.C 把jec汇编成abel文件-GAL16V8 disassemble source JED2ABEL.C the JEC document compiled abel
- 2022-03-24 15:17:02下载
- 积分:1
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pipeline_FPGA
FPGA流水线设计的资料,可以作为学习FPGA开发并行操作的一个经典教材,具有很好的指导作用。(FPGA pipeline design information can be developed as a learning FPGA parallel operation of a classic textbook, has a good guide.)
- 2011-07-02 12:00:57下载
- 积分:1
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扩频通信的Verilog工程
扩频通信的Verilog工程,对从事无线通信的工程人员有参考作用。(Spread spectrum communication Verilog project, engaged in wireless communications engineering staff reference.)
- 2017-06-11 10:29:12下载
- 积分:1
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add
流水线乘法器与加法器
开发环境:Modelsim(verilog hdl)(Multiplier and adder pipeline development environment: Modelsim (verilog hdl))
- 2009-05-18 12:19:24下载
- 积分:1
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VHDL design classic, it is also useful.
VHDL经典设计,值得参考。压缩包里面文件直接用记事本打开即可。-VHDL design classic, it is also useful.
- 2022-05-26 21:13:44下载
- 积分:1
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JJ213_program
卷积码(213)的编译码,VHDL语言编写的整个工程文件,带有仿真结果图。(Convolution code (213) codec, VHDL language of the whole project file with the simulation results shown in Fig.)
- 2020-12-27 19:29:02下载
- 积分:1
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LDPC_DECODER(matlab)
本程序是在AWGN下的LDPC码的仿真程序,本程序优点是译码效率高,速率很快,可以仿帧数很大的图。(the decoder for LDPC under the AWGN channel)
- 2020-12-27 21:49:02下载
- 积分:1
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gtx
ip core of the transceiver gtx
- 2019-04-02 00:10:03下载
- 积分:1